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參數(shù)資料
| 型號： | W229B |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 183K |
| 代理商： | W229B |
W229B
Document #: 38-07223 Rev. *A
Page 15 of 17
Layout Example
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
6
7
8
9
10
13
14
15
16
17
18
19
20
21
24
25
26
27
28
G = VIA to GND plane layer V =VIA to respective supply plane layer
Note:
1) Each supply plane or strip should have a ferrite bead and capacitors.
2) Bypass capacitors are 0.1
μ
F ceramic unless otherwise stated.
3) C7 and C8 can be used to correct the crystal oscillaotr frequency if the crystal used is specified for more then
4) If an on-board video controler uses 48 MHz then use R1 and C5 to reduce long-term jitter on the 48 MHz clock.
VDDQ3, as shown, or to +3.3V supply.
R1 can connect to
G
+2.5V Supply
1
2
3
4
5
11
12
22
23
40
39
38
31
30
29
36
35
34
33
32
37
C
C
FB
+3.3V Supply
C4
C1 & C3 = 10
–
22
μ
F
C2 & C4 = 0.005
μ
F
10
μ
F
FB
C1
C2
FB = Vishay Dale ILB1206 - 300 (300
@ 100 MHz) or TDK ACB2012L120
0.005
μ
F
G
G
G
G
VDDQ2
VDDQ3
C3
C5 = 10
μ
F
C6 = 0.1
μ
F
G
10
VDDQ3
C5
C6
G
V
G
G
V
G
V
G
V
G
V
G
V
G
G
V
G
V
G
V
G
W
Core
VDDQ3
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
10
μ
F
0.005
μ
F
*Note 3
R1
*Note 4
G
18 pF Cload.
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