
W229B
Document #: 38-07223 Rev. *A
Page 3 of 17
Overview
The W229B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel
architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Pin # 3, 11, 12, 13, 23, and 24 are dual-purpose l/O pins. Upon
power-up the pin acts as a logic input. An external 10-k
strap-
ping resistor should be used.
Figure 1
shows a suggested
method for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Offsets Among Clock Signal Groups
Figure 2
,
Figure 3
, and
Figure 4
represent the phase relation-
ship among the different groups of clock outputs from W229B
when it is providing a 66-MHz CPU clock, a 100-MHz CPU
clock, and a 133-MHz CPU clock, respectively. It should be
noted that when CPU clock is operating at 100 MHz, CPU
clock output is 180 degrees out of phase with SDRAM clock
outputs.
Power Down Control
W229B provides one PWRDWN# signal to place the device in
low-power mode. In low-power mode, the PLLs are turned off
and all clock outputs are driven LOW.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Output
Low
Q
D
W229B
Clock Load
Output
10 k
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option.
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
0 ns
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock).
40 ns
30 ns
20 ns
10 ns
SDRAM 100 Period
CPU 100 Period
Hub-PC