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參數(shù)資料
| 型號(hào)： | W229B |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大小： | 183K |
| 代理商： | W229B |
W229B
Document #: 38-07223 Rev. *A
Page 5 of 17
Notes:
2.
3.
4.
5.
Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W229B.
The shaded sections on the SDRAM, REF, and USB clocks indicate
“
Don
’
t Care
”
states.
Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
CPU 100-MHz
SDRAM 133-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
APIC 33-MHz
Cycle Repeat
Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM).
0 ns
40 ns
30 ns
20 ns
10 ns
1
2
Center
0ns
25ns
50ns
75ns
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 6. W229B PWRDWN# Timing Diagram
[2, 3, 4, 5]
.
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