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參數(shù)資料
| 型號(hào)： | W229B |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大小： | 183K |
| 代理商： | W229B |
W229B
Document #: 38-07223 Rev. *A
Page 9 of 17
W229B Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be writ-
ten to a
“
0
”
level.
3. All register bits labeled
“
Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current. The controller will read
back the written value.
Note:
8.
Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Byte 0: Control Register (1 = Enable, 0 = Disable)
[8]
Bit
Pin#
-
-
-
-
-
24
22, 23
-
Name
Default
0
0
0
0
0
1
1
0
Pin Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
SIO/24_48 MHz
48 MHz
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(Active/Inactive)
(Active/Inactive)
Reserved
Byte 1: Control Register (1 = Enable, 0 = Disable)
[8]
Bit
Pin#
38
41
42
43
44
47
48
49
Name
Default
1
1
1
1
1
1
1
1
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0 = Disable)
[8]
Bit
Pin#
20
19
18
16
15
13
12
11
Name
Default
1
1
1
1
1
1
1
1
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
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