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參數(shù)資料
| 型號： | W229B |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 183K |
| 代理商： | W229B |
W229B
Document #: 38-07223 Rev. *A
Page 2 of 17
I
Pin Definitions
Pin Name
REF2x/FS3*
Pin No.
3
Pin
Type
I/O
Pin Description
Reference Clock with 2x Drive/Frequency Select 3:
3.3V 14.318-MHz clock out-
put. This pin also serves as the select strap to determine device operating frequency
as described in
Table 1
.
Crystal Input:
This pin has dual functions. It can be used as an external 14.318-
MHz crystal connection or as an external reference frequency input.
Crystal Output:
An input connection for an external 14.318-MHz crystal connec-
tion. If using an external reference, this pin must be left unconnected.
PCI Clock 0/Frequency Selection 0:
3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1
.
PCI Clock 1/Frequency Selection 1:
3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1
.
PCI Clock 2/Frequency Selection 2:
3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1
.
PCI Clock 3 through 7:
3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually
turned off via SMBus interface.
66-MHz Clock Output:
3.3V output clocks. The operating frequency is controlled
by FS0:4 (see
Table 1
).
48-MHz Clock Output
: 3.3V fixed 48-MHz, non-spread spectrum clock output.
48-MHz Clock Output/Frequency Selection 4:
3.3V fixed 48-MHz, non-spread
spectrum clock output. This pin also serves as the select strap to determine device
operating frequency as described in
Table 1
.
Clock Output for Super I/O:
This is the input clock for a Super I/O (SIO) device.
During power up, it also serves as a selection strap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.
Power Down Control:
LVTTL-compatible input that places the device in power-
down mode when held LOW.
CPU Clock Outputs:
Clock outputs for the host bus interface. Output frequencies
depending on the configuration of FS0:4. Voltage swing is set by VDDQ2.
SDRAM Clock Outputs:
3.3V outputs for SDRAM and chipset. The operating fre-
quency is controlled by FS0:4 (see
Table 1
).
X1
4
I
X2
5
I
PCI0/FS0*
11
I/O
PCI1/FS1*
12
I/O
PCI2/FS2*
13
I/O
PCI3:7
15, 16, 18, 19,
20
7, 8, 9
O
3V66_0:2
O
48MHz_0
48MHz_1/
FS4*
22
23
O
I/O
SIO/
24_48MHz#*
24
I/O
PWRDWN#
30
I
CPU0:1
52, 51
O
SDRAM0:12,
49, 48, 47, 44,
43, 42, 41, 38,
37, 36, 35, 32,
31
55
O
APIC
O
Synchronous APIC Clock Outputs:
Clock outputs running synchronous with the
PCI clock outputs. Voltage swing set by VDDQ2.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
3.3V Power Connection:
Power supply for SDRAM output buffers, PCI output buff-
ers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
3.3V Power Connection:
Power supply for PLL core.
2.5V Power Connection:
Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
Ground Connections:
Connect all ground pins to the common system ground
plane.
SDATA
SCLK
VDDQ3
26
29
I/O
I
P
2, 6, 17, 25, 34,
40, 46
28
53, 56
VDD3
VDDQ2
P
P
GND
1, 10, 14, 21, 27,
33, 39, 45, 50,
54
G
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