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參數(shù)資料
| 型號： | W65C134S8Q-8 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 711K |
| 代理商： | W65C134S8Q-8 |
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WESTERN DESIGN CENTER
W65C134S
March 1, 2000
12
1.10.2 Asynchronous Receiver Operation
The receiver and its selected control and status functions are enabled when ACSR5 is set to a "1".
The Receiver Data Register (ARTD) is located at $0023. The data format must have a start bit, 7 or
8 data bits, and one stop bit or one parity bit and one stop bit. The receiver bit period is divided into
16 sub-intervals for internal synchronization. The receiver bit stream is synchronized by the start bit,
and a strobe signal is generated at the approximate center of each incoming bit. The character
assembly process does not start if the start bit signal is less than one-half the bit time after a low level
is detected on the Receive Data Input. A framing error, parity error or an over-run will set ASCR7,
the receiver error detection bit. An over-run condition occurs when the receiver data register has not
been read and new data byte is transferred from the receiver shift register.
Serial
Data
Start
Bit
0
1
2
3
4
5
6
Stop
Bit
Stop
Bit
Note:
The receiver requires only one stop bit but the transmitter supplies two stop bits for older system
timing.
Figure 1-8 Asynchronous Receiver Data Timing
A receiver interrupt (IRQAR) is generated whenever the receiver shift register is transferred to the
receiver data register.
1.10.3 Asynchronous Control and Status Register (ACSR)
The Asynchronous Control and Status Register (ACSR) enables the Receiver and Transmitter and
holds information on communication status error conditions.
Bit assignments and function of the ACSR are as follows:
ACSR0:
Transmitter Enable. The Asynchronous Transmitter is enabled, the Transmitter
Interrupt (IRQAT), and TXD is enabled on P61 when ACSR0=1. When ACSR0 is
cleared, the ACSR1 is cleared, the transmitter will be disabled, the Transmitter Interrupt
will not occur and TXD will be disabled on P61. This bit is cleared by a RESET.
Transmitter Interrupt Source Select. When ACSR1=0, the Transmitter Interrupt occurs
due to a Transmitter Data Register Empty condition (end-of-byte transmission). When
ACSR1=1 the Transmitter Interrupt occurs due to both the Transmitter Data and Shift
register empty condition (end-of-message transmission). The Transmitter Interrupt is
cleared by writing to the Transmitter Data Register ($0023), or by a RESET.
Seven or Eight-Bit Data Select. When ACSR2=0, the Transmitter and Receiver send
and receive 7-bit data. The Transmitter sends a total of 10 bits of information (one start,
7 data, one parity and one stop or 2 stop bits). The Receiver receives 9 or 10 bits of
information (one start, 7 data, and one stop or one stop and one parity bits).
ACSR1:
ACSR2:
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相關代理商/技術參數(shù) |
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| W65C21N6TPLG-14 | 功能描述:外圍驅動器與原件 - PCI Peripheral Interface Adapter RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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