參數(shù)資料
型號: W65C134S8Q-8
元件分類: 8位微控制器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁數(shù): 7/60頁
文件大?。?/td> 711K
代理商: W65C134S8Q-8
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
2
SECTION 1
W65C134S FUNCTION DESCRIPTION
1.1
The W65C02S Static 8-bit Microprocessor Core
The W65C02S 8-bit microprocessor is the fully static (may be stopped when PHI2 is high or low) version of the
popular W65C02S microprocessor used in the Apple IIc and IIe personal computer systems. The W65C02S is
compatible with the NMOS 6502 used in many control applications and personal computers. The small die size and
low power consumption of the W65C02S offer an excellent choice as a cost effective core microprocessor in
one-chip microcomputers. The W65C02S instruction set is compatible with the W65C802S and W65C816S, 16-bit
microprocessors and the W65C832S, 32-bit microprocessor.
1.2
4096 x 8 ROM
The W65C134S 4096 x 8 bit Read Only Memory (ROM) usually contains the user's program instructions and other
fixed constants. These program instructions and constants are mask-programmed into the ROM during fabrication
of the W65C134S device. The W65C134S ROM is memory mapped from $F000 to $FFFF.
1.3
192 x 8 RAM
The 192 x 8 bit Random Access Memory (RAM) contains the user program stack and is used for scratch pad
memory during system operation. This RAM is completely static in operation and requires no clock or dynamic
refresh. The data contained in RAM is read out nondestructively with the same polarity as the input data. In order
to take advantage of zero page addressing capabilities, the W65C134S RAM is assigned to both page zero memory
addresses $0040 to $00FF and to page one stack addresses $0140 to $01FF.
1.4
Bus Control Register (BCR) at memory address $001B
1.4.1
1.4.2
The Bus Control Register (BCR) controls the various modes of I/O and external memory interface.
During power-up the value of BE defines the initial values of BCR0, BCR3 and BCR7, three bits in
the BCR that set up the W65C134S for In-Circuit-Emulation (ICE) or test modes.
When BE goes high after RESB goes high the BCR sets up the W65C134S for emulation. Port 0 and
1 are the address outputs, Port 2 is the data I/O bus and RUN is the multiplexed RUN function. (see
RUN pin function description).
When BE goes high before RESB goes high, all bits in the BCR are "0".
After RESB goes high BE no longer effects the BCR register, and BCR may be written under
software control to reconfigure the W65C134S as desired.
1.4.6
Table 1-1 indicates how BCR7 and BE define the W65C134S configuration.
1.4.3
1.4.4
1.4.5
Table 1-1 BCR7 and BE Control
BCR7
BE
W65C134S Configuration
0
0
Internal ROM External Processor (DMA)
0
1
Internal ROM Internal Processor
1
0
External ROM External Processor (DMA)
1
1
External ROM Internal Processor
Figure 1-1 BE Timing Relative to RESB Input
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