參數(shù)資料
型號(hào)： W65C134S8Q-8
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁數(shù)： 22/60頁
文件大小： 711K
代理商： W65C134S8Q-8
WESTERN DESIGN CENTER
1.11.4 Sequence of events for the SIB message transmission.
W65C134S
March 1, 2000
17
1.11.4.1
State 0 events (STATE=$01) The SIB controllers wait for some device to request
mastery. All devices on the serial bus wait for one or more devices to request
mastery. At any time any processor with data to send sets SCSR0 (write pending)
and the SIB is in state 0 (STATE=$01) then the following occurs:
1. SCLK stops running.
2. Each device with SCSR0=1 pulls SDAT low to request SCLK.
3. SCLK restarts and advances the state machine to state 1 (STATE=$02).
State 1 events (STATE=$02)
The SIB controllers establish mastery for this message. State 1 determines which
devices is master for this message and insures that SDAT is high on transition to
state 2 (STATE=$04) in state 1 (STATE=$02) the following occurs:
1. The device that was master just before transition to state 1 sets SCSR2
(previous master), and all other devices reset SCSR2.
2. The device with SCSR2 set to a "1" makes its CHOUT high. Other devices only
make CHOUT high if both their CHIN is high and SCSR0=0. Thus the first
device in the chain after the previous master that has write pending (SCSR0=1)
is the master for this message.
3. The device that is master for this message outputs a high level on SDAT.
4. SCLK advances to state 2 (STATE=$04).
State 2 events (STATE=$04)
The master's SIB controller waits for data from its processor. The SIB waits in
state 2 (STATE=$04) for the master to load its data and the following occurs:
1. SCLK stops running.
2. The SIB controller that is master sets SCSR7 to interrupt and signal its
processor that it has acquired mastery.
3. In response to the interrupt the processor should:
a)
check "read pending" (SCSR4) to see if it has received a message before
acquiring mastery, and if so read it, thus clearing SCSR4;
b)
check "message not acknowledged" SCSR3 to see if the last message it sent
was not acknowledged;
c)
place the data it wants to send in SR0, SR1, SR2, and SR3, and;
d)
clear "write pending" SCSR0 to signal the SIB controller that data is there
to send. This happens on the trailing edge of the write to SR0 so SR0 must
be the last byte written into the shift register.
4. The master pulls SDAT low to request SCLK.
5. After at least one-half-cycle, SCLK advances the state counter to state 3
(STATE=$08).
States 3 through 34 events (STATE=$08)
The message is sent. During state 3 through 34 (STATE=$08) the SIB transfers the
message from the master's shift register to all devices that have read their previous
messages.
1. Any device that had "read pending" (SCSR4=1) just before transition to state 3
sets "deaf" SCSR5, so that it cannot receive the incoming message on top of the
one its processor has not read.
2. While in state 3-34 (STATE=$08) the device that is master sends its
shift-register data output onto SDAT.
1.11.4.2
1.11.4.3
1.11.4.4
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