參數(shù)資料
型號(hào)： W65C134SPL-8
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 16/60頁(yè)
文件大?。?/td> 711K
代理商： W65C134SPL-8
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
11
1.10 Universal Asynchronous Receiver/Transmitter (UART)
The W65C134S Microcomputer provides a full duplex Universal Asynchronous Receiver/Transmitter (UART) with
programmable bit rates. The serial I/O functions are controlled by the Asynchronous Control and Status Register
(ACSR). The ACSR bit assignment is shown in Figure 1-9. The serial bit rate is determined by Timer A for all
modes. The maximum data rate using the internal clock is 62.5K bits per second (PHI2 = 1MHz). The
Asynchronous Transmitter and Asynchronous Receiver can be independently enabled or disabled. All transmitter
and receiver bit rates will occur at one sixteenth of the Timer A interval timer rate. Timer A is forced into an
interval timer mode whenever the serial I/O is enabled.
Whenever Timer A is required as a timing source, it must be loaded with the hexadecimal code that selects the data
rate for the serial I/O Port. Refer to Table 1-2 for a table of hexadecimal values that represent the desired data rate.
WDC Standard UART Features
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7 or 8 bit data with or without Odd or Even parity.
The Transmitter has 1 stop bit with parity or 2 stop bits without parity.
The Receiver requires only 1 stop bit for all modes.
Both the Receiver and Transmitter have priority encoded interrupts for service routines.
The Receiver has error detection for parity error, framing error, or over-run error conditions that may require
re-transmission of the message.
The Receiver Interrupt occurs due to a receiver data register full condition.
The Transmitter Interrupt can be selected to occur on either the data register empty (end-of-byte transmission)
or both the data register empty and the shift register empty (end-of-message transmission) condition.
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1.10.1 Asynchronous Transmitter Operation
The transmitter operation is controlled by the Asynchronous Control and Status Register (ACSR).
The transmitter automatically adds a start bit, parity bit and one or two stop bits as defined by the
ACSR. A word of transmitted data is 7 or 8 bits of data.
The Transmitter Data Register (ARTD) is located at address $0023 and is loaded on a write. The
Receiver is read at this same address.
Serial
Data
Start
Bit
0
1
2
3
4
5
6
7
Parity
Bit
Stop
Bit
The Transmitter Interrupt is controlled by the Asynchronous Control Status Register bit ACSR1.
IRQAT =ACSR0((ACSR1B)(DATA REGISTER EMPTY) + (ACSR1)(DATA REGISTER AND SHIFT
REGISTER EMPTY))
Figure 1-7 Asynchronous Transmitter Mode with Parity
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W65C134SQ-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
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W65C21N6TPLG-14 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Peripheral Interface Adapter RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
W65C21S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral Interface Adapter (PIA)
W65C21S6TPG-14 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Peripheral Interface Adapter RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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