參數(shù)資料
型號(hào)： W65C134SPL-8
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 21/60頁(yè)
文件大?。?/td> 711K
代理商： W65C134SPL-8
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
16
1.11.3.2
SCSR2 is the "previous master" control and status bit. When SCSR2 is set to a "1",
this means that the SIB was master before the last time mastery changed. One
device is chosen as previous master (one MPU on the network writes a "1" to
SCSR2) before the first message is sent. SCSR2 is set to a "1" for one SIB on the
network as part of system initialization upon power up or reset. This bit is ignored
during normal system operation.
SCSR3 is the "message not acknowledged" status bit of SCSR. When SCSR3 is set
to a "1" by the SIB logic due to SDAT equals a "1" during timing state 36, this
means that the last message this SIB sent was not acknowledged by the receiver
whose address matches the Bus Address Register (BAR) field of the message
(SR35, SR36 and SR37).
SCSR4 is the "read pending" status bit of the SCSR. When SCSR4 is set to a "1"
due to a match between the incoming message BAR field with the BAR, this means
that the SIB has received a message but its processor has not yet finished reading it.
It is reset when SR3, the last byte of the message, is read.
SCSR5 is the "deaf" status bit of the SIB. When SCSR5 is set to a "1" this means
that the SIB cannot receive a message in progress because when the message started,
its processor had not read its previous message.
SCSR6 is the "serial clock enable" control bit of SCSR. When SCSR6 is set to a
"1" by the on-chip MPU this means that the serial clock generator (PHI2) in this
device is enabled and provides the serial clock (SCLK) for the system. SCSR6 is set
to a "1" for one SIB on the network as part of system initialization upon power up or
reset. It is not used as part of the normal communication sequence.
SCSR7 is the SIB interrupt flag bit that is set by a SIB interrupt condition and reset
to zero by a write of a "1" to SCSR7. A write of a "0" has no effect on SCSR7.
1.11.3.3
1.11.3.4
1.11.3.5
1.11.3.6
1.11.3.7
SCSR ($0019)
7
6
5
4
3
2
1
0
SIB Write Pending
SIB Master
SIB Previous Master
SIB Message Not Acknowledged
SIB Read Pending
SIB Deaf
SIB Serial Clock Enable
SIBIRQ
Figure 1-12 SIB Control and Status Register (SCSR)
The SIB causes a SIBIRQ (SIB interrupt) when the SIB enable bit of the Bus Control Register is set (BCR2=1) and
SCSR1=1 (SIB master is set), or SCSR3=1 ISIB message not acknowledged), or SCSR4=1 (reading pending).
SIBIRQ=BCR2
C
(SCSR1+SCSR3+SCSR4)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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