參數(shù)資料
型號： W65C134SPL-8
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁數(shù)： 23/60頁
文件大小： 711K
代理商： W65C134SPL-8
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
18
3. Any device that does not have "deaf" SCSR5 set, including the master, advances
its shift register, on SCLK positive transitions, thus acquiring the data that was
in the master's shift-register.
4. SCLK advances the state counter to state 35 (STATE=$10).
State 35 events (STATE=$10)
The SIB is prepared for acknowledgement. State 35 (STATE=$10) is for the master
to insure that SDAT is high on entry to state 36 (STATE=$20). The device that is
master outputs a high level on SDAT. SCLK advances the state counter to state 36
(STATE=$20).
State 36 events (STATE=$20)
The receive should acknowledge its receipt of the message in state 36
(STATE=$20). When asserted, the destination device (the device that has
SR37,SR36,SR35 equal to BAR2,BAR1,BAR0 and "deaf" SCSR5=0) pulls SDAT
low to acknowledge reception to the master. SCLK advances the state counter to
state 37 (STATE=$40).
State 37 events (STATE=$40)
The MPU's are interrupted with the result of transmission in the SR's. State 37
(STATE=$40) is for the master to interrupt and signal its processor if the message it
sent was not acknowledged, for the receiver to interrupt and signal its processor that
a message is available to read, and for the master to insure that SDAT is high on
transition to state 0 (STATE=$01). In state 37 (STATE=$40) the following occurs:
1. If the master saw SDAT high just before the transition to state 37
(STATE=$40) (meaning there was no acknowledgement) then it sets SCSR3
"message not acknowledged" to interrupt and signal its processor that the
message was not received. If the master saw SDAT low just before the
transition to state 37 (STATE=$40) (meaning there was acknowledgement) then
SCSR3 is cleared and does not interrupt its processor.
2. The device with SCSR5=0 that has the SR37,6,5=BAR2,1,0 (message with its
address), sets SCSR4 "read pending" to interrupt and signal its processor that a
message is pending.
3. The master outputs a high level on SDAT for the duration of state 37
(STATE=$40).
4. SCLK advances the state counter to state 0 (STATE=$01).
Message processing may now be performed by the receiver. The message is read by
the receiver's processor in response to the SIB interrupt (SIBIRQ) generated by
SCSR4 "read pending", by reading the message in its shift register, and when
finished clears SCSR4 "read pending" (on the trailing edge of the read of SR3).
1.11.4.5
1.11.4.6
1.11.4.7
1.11.4.8
The message may now be processed.
The next message may now be sent on the SIB.
1.11.5 Bus Address Register (BAR)
The Bus Address Register (BAR) contains the address that is used by the receive function logic of
the SIB to compare against the "address field" (SR37,SR36 and SR35) of the Shift Register
incoming data. When the BAR address matches the "address field" of the Shift Register the host
is interrupted indicating that a "message has been received".
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相關代理商/技術參數(shù)
參數(shù)描述
W65C134SQ-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
W65C21N6TPG-14 功能描述:外圍驅(qū)動器與原件 - PCI Peripheral Interface Adapter RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
W65C21N6TPLG-14 功能描述:外圍驅(qū)動器與原件 - PCI Peripheral Interface Adapter RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
W65C21S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral Interface Adapter (PIA)
W65C21S6TPG-14 功能描述:外圍驅(qū)動器與原件 - PCI Peripheral Interface Adapter RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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