參數(shù)資料
型號: W742E811
文件頁數(shù): 25/66頁
文件大?。?/td> 303K
代理商: W742E811
Preliminary W742C(E)811
Publication Release Date: May 1999
- 25 -
Revision A1
Q1
Q2
Q9
Q10 Q11 Q12
Q14
Q13
Fosc
S
R
Q
HEF.0
IEF.0
1. Reset
2. CLR EVF,#01H
3. CLR DIVR0
EVF.0
Hold mode release (HCF.0)
Divider interrupt
. . .
Overflow signal
WDT
Enable
Disable
SCR.2
Fosc/1024
Fosc/16384
Option code is reset to "0"
Qw1
R
Qw2
R
Qw4
R
Qw3
R
Divider0
System Reset
1. Reset
2. CLR WDT
Option code is set to "1"
Figure 5-5 Organization of Divider0 and Watchdog Ttimer
5.12 Timer/Counter
5.12.1 Timer 0 (TM0)
Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0
by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TM0H),R instructions are
executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to 0, and
the specified value can be loaded into TM0. Then we can set MR0.3 to 1, that will cause the event flag 1
(EVF.1) is reset and the TM0 starts to down count. When it decrements to FFH, Timer 0 stops operating
and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag has been set (IEF.1 =
1), the interrupt is executed, while if the hold release enable flag 1 has been set (HEF.1 = 1), the hold
state is terminated. The Timer 0 clock input can be set as F
OSC
/1024 or F
OSC
/4 by setting MR0 bit 0.
The default timer value is F
OSC
/4. The organization of Timer 0 is shown in Figure 5-6.
If the Timer 0 clock input is F
OSC
/4:
Desired Timer 0 interval = (preset value +1)
×
4
×
1/F
OSC
If the Timer 0 clock input is F
OSC
/1024:
Desired Timer 0 interval = (preset value +1)
×
1024
×
1/F
OSC
Preset value: Decimal number of Timer 0 preset value
F
OSC
: Clock oscillation frequency
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