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Preliminary W742C(E)811

- 42 -

Figure 5-14 Architecture of Input Ports RC

5.19.1 Port Status Register 0 (PSR0)

Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or

cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

PSR0

Note: R means read only.

Bit 0 = 1 Signal change at RC.0

Bit 1 = 1 Signal change at RC.1

Bit 2 = 1 Signal change at RC.2

Bit 3 = 1 Signal change at RC.3

5.20 Input Ports RD

Port RD consists of pins RD.0 to RD.3. Each pin of port RD can be connected to a pull-high resistor,

which is controlled by the port mode 0 register (PM0). When the PEF and HEFD corresponding to the

RD port are set, a signal change at the specified pins of port RD will execute the hold mode release.

Port status register 1 (PSR1) records the status of signal changes on the pins of port RD. PSR1 can be

read out and cleared by the MOVA R, PSR1, and CLR PSR1 instructions. In addition, the falling edge

signal on the pin of port RD specified by the instruction MOV SEF, #I will cause the device to exit the

stop mode. Refer to Figure 5-15 and the instruction table for more details.

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