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| 型號(hào)： | W742E811 |
| 文件頁(yè)數(shù)： | 28/66頁(yè) |
| 文件大?。?/td> | 303K |
| 代理商： | W742E811 |
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Preliminary W742C(E)811
- 28 -
5.12.3 Mode Register 0 (MR0)
Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control
the operation of Timer 0. The bit descriptions are as follows:
Note: W means write only.
W
W
0
1
2
3
MR0
Bit 0 = 0 The fundamental frequency of Timer 0 is F
OSC
/4.
= 1 The fundamental frequency of Timer 0 is F
OSC
/1024.
Bit 1 & Bit 2 are reserved
Bit 3 = 0 Timer 0 stops down-counting.
= 1 Timer 0 starts down-counting.
5.12.4 Mode Register 1 (MR1)
Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control
the operation of Timer 1. The bit descriptions are as follows:
Note: W means write only.
W
W
W
W
0
1
2
3
MR1
Bit 0 = 0 The internal fundamental frequency of Timer 1 is F
OSC
.
= 1 The internal fundamental frequency of Timer 1 is F
OSC
/64.
Bit 1 = 0 The fundamental frequency source of Timer1 is the internal clock.
= 0 The fundamental frequency source of Timer1 is the sub-oscillator frequency Fs (32.768
KHz).
Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.
= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.
Bit 3 = 0 Timer 1 stops down-counting.
= 1 Timer 1 starts down-counting.
5.13 Interrupts
The W742C(E)811 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and
seven external interrupt source (port P1.2(/INT 0), RC.0-3, Serial port, P1.3(
INT1
)). Vector addresses for
each of the interrupts are located in the range of program memory (ROM) addresses 004H to 023H. The
flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the
corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an
interrupt occurs, the corresponding bit of EVF will be clear, and all of the interrupts will be inhibited until
the EN INT or MOV IEF,#I instruction is invoked. Normally, the EN INT instruction will be asserted before
the RTN instruction. The interrupts can also be disabled by executing the DIS INT instruction. When an
interrupt is generated in the hold mode, the hold mode will be released momentarily and interrupt service
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