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Preliminary W742C(E)811
Publication Release Date: May 1999
- 37 -
Revision A1
Input/Output Pin of the P0
I/O PIN
P0.n
DATA
BUS
Buffer
Output
PM6.n
MOVA R,P0 instruction
MOV P0,R instruction
Enable
Enable
Figure 5-11 Architecture of P0 Input/Output pins
5.17.1 Port Mode 0 Register (PM0)
The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to
determine the port structure; it is controlled by the MOV PM0, #I instruction. The bit description is as
follows:
PM0
Note: W means write only.
w
w
w
0
1
2
w
3
Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type.
Bit 1 = 0 RB port is CMOS output type. Bit 1 = 1 RB port is NMOS open drain output type.
Bit 2 = 0 RC port pull-high resistor is disabled. Bit 2 = 1 RC port pull-high resistor is enabled.
Bit 3 = 0 RD port pull-high resistor is disabled. Bit 3 = 1 RD port pull-high resistor is enabled.
5.17.2 Port Mode 1 Register (PM1)
The port mode 1 register is organized as 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to
control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit
description is as follows:
PM1
Note: W means write only.
w
w
w
0
1
2
w
3
Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin
Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin
Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin
Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin
At initial reset, port RA is input mode (PM1 = 1111B).