參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 126/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Min. Grant (3Eh) and Max. Latency (3Fh) Registers
These read-only registers specify the desired latency timer value. They each represent a number of 1/4 microsecond time
units.
The Min Grant is the time required to complete a worst case burst assuming a 33MHz PCI clock. The hard coded value is
02h which represents 0.5μs.
The Max Latency specifies how often the W83C553F needs to gain control of the PCI bus. The hard coded value is 28h
which represents 10μs.
Electrical Specifications
WINBOND SYSTEMS LABORATORY
123
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