參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 133/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
4.4
The Bus Master IDE Register set is defined by the PCI SIG. It is composed of 16 8-bit registers and is located at the I/O
address specified by Base Address Register 4. The registers can be accessed 8, 16, 24, or 32 bits at a time.
This register set is supplied to offer a higher performance lower overhead IDE disk protocol. With this protocol, the host
(PCI) transfers will be bus master cycles and the IDE device transfers will be DMA. The normal PIO protocol uses I/O
transfers on both the host and IDE interfaces. Primary and Secondary refer to the primary and secondary IDE ports. Both
register sets are identical.
Table 4-5
.
Bus Master IDE I/O Register Organization
Offset from
Base Address
31
24
23
Electrical Specifications
WINBOND SYSTEMS LABORATORY
130
Bus Master IDE (Function 1) I/O Registers
Register Bits
16
15
8
7
Primary Command
Register
0
03h - 00h
Reserved
Primary Status
Register
Reserved
07h - 04h
Reserved
Primary PRD Table Address
0Bh - 08h
Secondary Status
Register
Reserved
Secondary Command
Register
0Fh - 0Ch
Secondary PRD Table Address
Note: The registers shown in Table 4-5
cannot be accessed
until after Base Address Register 4 is written (with any non zero
value).
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