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參數(shù)資料
| 型號(hào)： | W947D6HBHX5E |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60 |
| 文件頁數(shù)： | 39/60頁 |
| 文件大?。?/td> | 1160K |
| 代理商： | W947D6HBHX5E |
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W947D6HB / W947D2HB
128Mb Mobile LPDDR
Publication Release Date:Jun,17, 2011
- 44 -
Revision A01-003
7.13 Deep Power Down
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the
LPDDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and
the Extended Mode Register is lost.
Deep Power-Down is entered using the BURST TERMINATE command
except that CKE is registered Low. All
banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this state, CKE
must be held in a constant Low state.
To exit the DPD mode, CKE is taken high after the clock is stable and NOP commands must be maintained for at
least 200
μs. After 200μs a complete re-initialization is required following steps 4 through 11 as defined for the
initialization sequence.
7.13.1 Deep Power-Down Entry and Exit
tRP
T=200us
Exit DPD
Mode
Enter DPD
Mode
= Don't Care
1) Clock must be stable before exiting Deep Power-Down mode. That is, the clock must be cycling
within specifications by Ta0
2) Device must be in the all banks idle state prior to entering Deep Power-Down mode
3) 200us is required before any command can be applied upon exiting Deep-Down mode
4) Upon exiting Deep Power-Down mode a PRECHARGE ALL command must be issued, followed
by two REFRESH commands and a load mode register sequence
NOP
DPD
NOP
Valid
Ta2
Ta1
Ta0
T0
T1
CK
CKE
Command
Address
DQS
DQ
DM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WS57C256F-70LMB | 32K X 8 UVPROM, 70 ns, CQCC32 |
| WMS128K8C-120FEIEA | 128K X 8 STANDARD SRAM, 120 ns, CDFP32 |
| WMS128K8L-100FEIE | 128K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| WMS128K8L-120FECEA | 128K X 8 STANDARD SRAM, 120 ns, CDFP32 |
| WMS128K8L-120DRIEA | 128K X 8 STANDARD SRAM, 120 ns, CDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W947D6HBHX5I | 制造商:WINBOND 制造商全稱:Winbond 功能描述:128Mb Mobile LPDDR |
| W947D6HBHX5I TR | 制造商:Winbond Electronics Corp 功能描述: |
| W947D6HBHX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPDDR SDRAM 128MBIT 60VFBGA |
| W947D6HBHX6G | 制造商:WINBOND 制造商全稱:Winbond 功能描述:128Mb Mobile LPDDR |
| W948D2FB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:256Mb Mobile LPDDR |
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