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參數(shù)資料
| 型號(hào)： | W947D6HBHX5E |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60 |
| 文件頁數(shù)： | 44/60頁 |
| 文件大?。?/td> | 1160K |
| 代理商： | W947D6HBHX5E |
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W947D6HB / W947D2HB
128Mb Mobile LPDDR
Publication Release Date:Jun,17, 2011
- 49 -
Revision A01-003
(128Mb, X32)
PARAMETER
SYMBOL
TEST CONDITION
- 5
- 6
- 75
UNIT
Operating one
bank active-
precharge current
IDD0
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH;
CS is HIGH between valid
commands; address inputs are SWITCHING; data bus inputs are
STABLE
40
38
35
mA
Precharge power-
down standby
current
IDD2P
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin ;
address and control inputs are SWITCHING; data bus inputs
are STABLE
Low
power
0.23
mA
Normal
power
0.28
Precharge power-
down standby
current with clock
stop
IDD2PS
all banks idle, CKE is LOW;
CS is HIGH, CK = LOW,
= HIGH; address and control inputs are SWITCHING;
data bus inputs are STABLE
Low
power
0.23
mA
Normal
power
0.28
Precharge non
power-down
standby current
IDD2N
all banks idle, CKE is HIGH;
CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus
inputs are STABLE
10
mA
Precharge non
power-down
standby current
with clock stop
IDD2NS
all banks idle, CKE is HIGH;
CS is HIGH, CK = LOW,
= HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE
3
mA
Active power-
down standby
current
IDD3P
one bank active, CKE is LOW;
CS is HIGH, tCK = tCKmin; address
and control inputs are SWITCHING; data bus inputs are STABLE
3
mA
Active power-
down standby
current with clock
stop
IDD3PS
one bank active, CKE is LOW;
CS is HIGH, CK = LOW,
= HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
3
mA
Active non
power-down
standby current
IDD3N
one bank active, CKE is HIGH;
CS is HIGH, tCK = tCKmin; address
and control inputs are SWITCHING; data bus inputs are STABLE
25
20
mA
Active non
power-down
standby current
with clock stop
IDD3NS
one bank active, CKE is HIGH;
CS is HIGH, CK = LOW,
=
HIGH; address and control inputs are SWITCHING; data bus inputs are
STABLE
15
12
mA
Operating burst
read current
IDD4R
one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts;
IOUT = 0 mA; address inputs are SWITCHING; 50% data change each
burst transfer
75
70
mA
Operating burst
write current
IDD4W
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change
each burst transfer
55
50
mA
Auto-Refresh
Current
IDD5
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data bus inputs are
STABLE
50
mA
Deep Power-
Down current
IDD8(4)
Address and control inputs are STABLE; data bus inputs are STABLE
10
uA
Notes:
1.
IDD specifications are tested after the device is properly initialized.
2.
Input slew rate is 1V/ns.
3.
Definitions for IDD:
LOW is defined as VIN ≤ 0.1 * VDDQ;HIGH is defined as VIN
≥ 0.9 * VDDQ;STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- Address and command: inputs changing between HIGH and LOW once per two clock cycles;
- Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
4.
IDD8 are typical value at 25℃.
CK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WS57C256F-70LMB | 32K X 8 UVPROM, 70 ns, CQCC32 |
| WMS128K8C-120FEIEA | 128K X 8 STANDARD SRAM, 120 ns, CDFP32 |
| WMS128K8L-100FEIE | 128K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| WMS128K8L-120FECEA | 128K X 8 STANDARD SRAM, 120 ns, CDFP32 |
| WMS128K8L-120DRIEA | 128K X 8 STANDARD SRAM, 120 ns, CDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W947D6HBHX5I | 制造商:WINBOND 制造商全稱:Winbond 功能描述:128Mb Mobile LPDDR |
| W947D6HBHX5I TR | 制造商:Winbond Electronics Corp 功能描述: |
| W947D6HBHX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPDDR SDRAM 128MBIT 60VFBGA |
| W947D6HBHX6G | 制造商:WINBOND 制造商全稱:Winbond 功能描述:128Mb Mobile LPDDR |
| W948D2FB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:256Mb Mobile LPDDR |
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