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參數(shù)資料
| 型號： | WED9LC6816V1312BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA153 |
| 封裝： | 14 X 22 MM, MO-163, BGA-153 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大小： | 324K |
| 代理商： | WED9LC6816V1312BC |
WED9LC6816V
21
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September, 2003
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIG. 13 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ
BURST STOP @ BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDRAS#
SDCAS#
ADDR
RAa
CAa
CAb
BA0, 1
[A12,A13]
SDA10
RAa
CL=2
QAa0 QAa1 QAa2 QAa3
Note 2 1
QAa4
QAb1
QAb0
QAb2 QAb3 QAb4 QAb5
CL=3
DQ
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
SDCE#
SDWE#
BWE#
1
2
NOTES:
1.
At full page mode, burst is end at the end of burst. So auto precharge is possible.
2.
About the valid DQs after burst stop, it is the same as the case of SDRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on
each of them. But at burst write, burst stop and SDRAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”.
3.
Burst stop is valid at every burst length.
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