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參數資料
| 型號： | WED9LC6816V1312BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA153 |
| 封裝： | 14 X 22 MM, MO-163, BGA-153 |
| 文件頁數： | 16/26頁 |
| 文件大小： | 324K |
| 代理商： | WED9LC6816V1312BC |
WED9LC6816V
23
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September, 2003
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @
BURST LENGTH = 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
RBb
CAb
CAd
CBc
BA0, 1
[A12,A13]
CL=2
QAb0
DAa0
QAb1
QAd0
DBc0
QAd1
QAa1
QAb1
DBc0
QAd1
QAd0
CL=3
DQ
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(Both Banks)
SDA10
RAa
RBb
SDWE#
DON’T CARE
RAc
BWE#
NOTES:
1.
BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is xed to “1” regardless of programmed burst length.
2.
When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so
in the case of BRSW write command, the next cycle starts the precharge.
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