- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄140416 > WED9LC6816V1312BC (WHITE ELECTRONIC DESIGNS CORP) SPECIALTY MEMORY CIRCUIT, PBGA153 PDF資料下載
參數(shù)資料
| 型號： | WED9LC6816V1312BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA153 |
| 封裝： | 14 X 22 MM, MO-163, BGA-153 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 324K |
| 代理商： | WED9LC6816V1312BC |
WED9LC6816V
12
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September, 2003
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
NOTES:
1.
Both Banks must be idle otherwise it is an illegal action.
2.
The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then
the action may be legal depending on the state of that bank.
3.
The minimum and maximum Active time (tRAS) must be satised.
4.
The RAS# to CAS# Delay (tRCD) must occur before the command is given.
5.
Address SDA10 is used to determine if the Auto Precharge function is activated.
6.
The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satised.
Current
State
Command
Action
Notes
SDCE#
SDRAS#
SDCAS#
SDWE#
A12 & A13
(BA)
A11-A0
Description
Write
Recovering
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
L
H
L
BA
Column
Write
Start Write; Determine if Auto Precharge
6
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
6
L
H
L
X
Burst Termination
No Operation; Row active after tDPL
L
H
X
No Operation
No Operation; Row active after tDPL
H
X
Device Deselect
No Operation; Row active after tDPL
Write
Recovering
with Auto
Precharge
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
L
H
L
BA
Column
Write
ILLEGAL
2,6
L
H
L
H
BA
Column
Read
ILLEGAL
2,6
L
H
L
X
Burst Termination
No Operation; Precharge after tDPL
L
H
X
No Operation
No Operation; Precharge after tDPL
H
X
Device Deselect
No Operation; Precharge after tDPL
Refreshing
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
No Operation; Idle after tRC
L
H
X
No Operation
No Operation; Idle after tRC
H
X
Device Deselect
No Operation; Idle after tRC
Mode
Register
Accessing
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self
Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
ILLEGAL
L
H
X
No Operation
No Operation; Idle after two clock cycles
H
X
Device Deselect
No Operation; Idle after two clock cycles
相關PDF資料 |
PDF描述 |
|---|---|
| W3EG2256M72ASSR202JD3SG | 512M X 72 DDR DRAM MODULE, 0.8 ns, DMA184 |
| W3EG2256M72ASSR263AJD3SG | 512M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3DG6463V10D2-S | 64M X 64 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168 |
| WF128K32-150G4I | 512K X 8 FLASH 12V PROM MODULE, 150 ns, CQFP68 |
| WF2M32-80G4TC | 8M X 8 FLASH 12V PROM MODULE, 80 ns, CQFP68 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WED9LC6816V1312BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 32 SSRAM/ 4M X 32 SDRAM |
| WED9LC6816V1510BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 32 SSRAM/ 4M X 32 SDRAM |
| WED9LC6816V1510BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 32 SSRAM/ 4M X 32 SDRAM |
| WED9LC6816V1512BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 32 SSRAM/ 4M X 32 SDRAM |
| WED9LC6816V1512BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 32 SSRAM/ 4M X 32 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。