參數(shù)資料
型號: WED9LC6816V1610BI
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA153
封裝: MO-163, BGA-153
文件頁數(shù): 8/27頁
文件大小: 370K
代理商: WED9LC6816V1610BI
16
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED9LC6816V
January 2001
FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
Rb
Cb0
Ca0
Ra
CL = 2
DQ
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tRCD
tRC
Rb
Note 1
Ra
Qa0
tSHZ
tRDL
tRAC
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
tSAC
tOH
Note 3
Note 4
Note 3
DON’T CARE
SDRAS
SDCAS
ADDR
BA
BWE
SDA10
SDCLK
SDCE
SDWE
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ)
after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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