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參數(shù)資料
| 型號： | WEDPNF8M721V-1210BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 19/42頁 |
| 文件大小： | 1297K |
| 代理商： | WEDPNF8M721V-1210BC |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
FD6 also toggles during erase-suspend-program mode, and
stops toggling once the Embedded Program algorithm is
complete.
Table 8 shows the outputs for “Toggle Bit I” on FD6. Figure
9 shows the Toggle Bit Algorithm. Figure 21 shows the toggle
bit timing diagrams. Figure 20 shows the difference between
FD2 and FD6 in graphical form. See also the subsection on
“FD2: Toggle Bit II”.
FD2: TOGGLE BIT II
The “Toggle Bit II” on FD2, when used with FD6, indicates
whether a particular sector is actively erasing (that is, the Em-
bedded Erase Algorithm is in progress) or whether that sec-
tor is erase-suspended. “Toggle Bit II” is valid after the rising
edge of the final FWE pulse in the command sequence.
FD2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either FOE or FCS to control the read
cycles.) FD2 cannot distinguish whether the sector is ac-
tively erasing or is erase-suspended. FD6, by comparison,
indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector
and mode information. Refer to Table 8 to compare out-
puts for FD2 and FD6.
Figure 9 shows the Toggle Bit Algorithm in flowchart form,
and the section “FD2: Toggle Bit II” explains the algorithm.
See also the subsection on “FD6: Toggle Bit I”. Figure 21
shows the toggle bit timing diagrams. Figure 20 shows the
difference between FD2 and FD6 in graphical form.
READING TOGGLE BITS FD6/FD2
Refer to Figure 9 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
FD7-FD0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on FD7-0 on the following
read cycle.
However, if after the initial two read cycles, the system de-
termines that the toggle bit is still toggling, the system also
should note whether the value of FD5 is high (see the sec-
tion on FD5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
RY/BY1: READY/BUSY
The RY/BY1 is a dedicated, open drain output pin that indi-
cates whether an Embedded Algorithm is in progress or
complete. The RY/BY1 status is valid after the rising edge of
the final FWE pulse in the command sequence. Since RY/
BY1 is an open-drain output, several RY/BY1 pins can be
tied together in parrallel with a pull-up resistor to Vcc.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase Sus-
pend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Sus-
pend mode.), or is in the standby mode.
Table 8 shows the outputs for RY/BY1. Figures 11, 12, 13,
19 show RY/BY1 for read, program, erase and reset opera-
tions, respectively.
FD6: TOGGLE BIT I
“Toggle Bit I” on FD6 indicates whether an Embedded Pro-
gram or Erase Algorithm is in progress or has been com-
pleted, or whether the device has entered the Erase Sus-
pend mode. Toggle Bit I may read at any address, and is
valid after the rising edge of the final FWE pulse in the com-
mand sequence (prior to the program or erase operation),
and during the sector erase time-out.
During an Embedded Program or Erase Algorithm opera-
tion, successive read cycles to any address will result in
FD6 toggling. (The system may use either FOE or FCS to
control the read cycles.) When operation is complete, FD6
stops toggling.
After the erase command sequence is written, if all selec-
tors selected for erasing are protected. FD6 toggles for ap-
proximately 100s, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
Algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use FD6 and FD2 together to determine whether
a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase Algo-
rithm is in progress) FD6 toggles. When the device enters the
Erase Suspend mode, FD6 stops toggling. However, the sys-
tem must also use FD2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use FD7 (see
the subsection on “FD7: Data Polling”).
If a program address falls within a protected sector, FD6
also toggles for approximately 1s after the program com-
mand sequence is written, then returns to reading array data.
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| WEDPNF8M721V-1210BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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