參數(shù)資料
型號(hào)： WEDPNF8M721V-1210BC
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類(lèi)： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 39/42頁(yè)
文件大?。?/td> 1297K
代理商： WEDPNF8M721V-1210BC
6
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 3)
(VCC = +3.3V ±0.3V; TA = -55°C TO +125°C)
Parameter/Condition
Symbol
Units
Min
Max
Supply Voltage
VCC
3
3.6
V
Input High Voltage: Logic 1; All inputs (4)
VIH
0.7 x Vcc
VCC + 0.3
V
Input Low Voltage: Logic 0; All inputs (4)
VIL
-0.3
0.8
V
SDRAM
Input Leakage Current: Any input 0V
VIN VCC
II
-5
5
A
(All other pins not under test = 0V)
SDRAM Input Leakage Address Current
(All other pins not under test = 0V)
II
-25
25
A
SDRAM Output Leakage Current: I/Os are disabled; 0V
VOUT VCC
IOZ
-5
5
A
SDRAM Output High Voltage (IOUT = -4mA)
VOH
2.4
–
V
SDRAM Output Low Voltage (IOUT = 4mA)
VOL
–
0.4
V
Flash
Flash Input Leakage Current (VCC = 3.6, VIN = GND or VCC)
ILI
10
A
Flash Output Leakage Current (VCC = 3.6, VIN = GND or VCC)
ILOx8
10
A
Flash Output High Voltage (IOH = -2.0 mA, VCC = 3.0)
VOH1
0.85 X VCC
V
Flash Output Low Voltage (IOL = 5.8 mA, VCC = 3.0)
VOL
0.45
V
Flash Low VCC Lock-Out Voltage (5)
VLKO
2.3
2.5
V
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Supply Voltage Range (VCC)
-0.5 to +4.0
V
Signal Voltage Range
-0.5 to Vcc +0.5
V
Operating Temperature TA (Mil)
-55 to +125
°C
Operating Temperature TA (Ind)
-40 to +85
°C
Storage Temperature, Plastic
-65 to +150
°C
Flash Endurance (write/erase cycles)
1,000,000 min.
cycles
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
SDRAM CAPACITANCE (NOTE 2)
Parameter
Symbol
Max
Unit
Input Capacitance: CLK
CI1
10
pF
Addresses, BA0-1 Input Capacitance
CA
35
pF
InputCapacitance:Allotherinput-onlypins
CI2
10
pF
Input/Output Capacitance: I/Os
CIO
12
pF
FLASH DATA RETENTION
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data
150°C
1 0
Years
Retention Time
125°C
2 0
Years
NOTES:
1. All voltages referenced to VSS.
2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
3. An initial pause of 100ms is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VCC must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
4. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width
3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width
3ns.
5. Guaranteed by design, but not tested.
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