參數(shù)資料
型號(hào)： WEDPNF8M721V-1210BC
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 20/42頁(yè)
文件大小： 1297K
代理商： WEDPNF8M721V-1210BC
27
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
FIG. 9 TOGGLE BIT ALGORITHM
1. Read toggle bit twice to detemine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as FD5 changes to 1.
See text.
have stopped toggling just as the device has successfully
completed the program or erase operation. If it is still tog-
gling, the device did not complete the operation success-
fully, and the system must write the reset command to re-
turn to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and FD5 has not gone high. The
system may continue to monitor the toggle bit and FD5 through
successive read cycles, determining the status as described
in the previous paragraph. Alternatively, it may choose to per-
form other system tasks. In this case, the system must start at
the beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 9).
FD5: EXCEEDED TIMING LIMITS
FD5 will indicate whether the program or erase time has
exceeded the specified limits (internal pulse count). Under
these conditions FD5 will produce a “1”. This is a failure
condition that indicates the program or erase cycle was not
successfully completed.
The FD5 failure condition may appear if the system tries to
program a “1” to a location that is previously programmed
to “0.” Only an erase operation can change a “0” back to a
“1.” Under this condition, the device halts the operation,
and when the operation has exceeded timing limits, the FD5
bit will produce a “1”.
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
FD3: SECTOR ERASE TIMER
After writing a sector erase command sequence, the system
may read FD3 to determine whether or not an erase opera-
tion has begun. (The sector erase timer does not apply to
the chip erase command.) If additional sectors are selected
for erasure, the entire time-out also applies after each addi-
tional sector erase command. When the time-out is com-
pleted, FD3 switches from “0” to “1.” The system may ignore
FD3 if the system can guarantee that the time between addi-
tional sector erase commands will always be less than 50s.
See also the “Sector Command Sequence” section.
After the sector erase command sequence is written, the
system should read the status on FD7 (Data Polling) or FD6
(Toggle Bit I) to ensure the device has accepted the com-
mand sequence, and then read FD3. If FD3 is high (“1”) the
internally controlled erase cycle has begun; all further com-
mands (other than Erase Suspend) will be ignored until the
erase operation is completed. If FD3 is low (“0”), the device
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