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參數(shù)資料
| 型號： | WEDPNF8M721V-1210BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 6/42頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | WEDPNF8M721V-1210BC |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
NOTES:
1. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range is ensured.
2. An initial pause of 100ms is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups
should be repeated any time the tREF refresh requirement is exceeded.
3. AC characteristics assume tT = 1ns.
4. In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
5. Outputs measured at 1.5V with equivalent load:
SDRAM AC FUNCTIONAL CHARACTERISTICS (NOTES 1,2,3,4,5,6)
Parameter/Condition
Symbol
-100
-125
Units
READ/WRITE command to READ/WRITE command (10)
tCCD
11
tCK
CKE to clock disable or power-down entry mode (7)
tCKED
11
tCK
CKE to clock enable or power-down exit setup mode (7)
tPED
11
tCK
DQM to input data delay (10)
tDQD
00
tCK
DQM to data mask during WRITEs
tDQM
00
tCK
DQM to data high-impedance during READs
tDQZ
22
tCK
WRITE command to input data delay (10)
tDWD
00
tCK
Data-in to ACTIVE command (8)
tDAL
45
tCK
Data-in to PRECHARGE command (9)
tDPL
22
tCK
Last data-in to burst STOP command (10)
tBDL
11
tCK
Last data-in to new READ/WRITE command (10)
tCDL
11
tCK
Last data-in to PRECHARGE command (9)
tRDL
22
tCK
LOAD MODE REGISTER command to ACTIVE or REFRESH command (11)
tMRD
22
tCK
Data-out to high-impedance from PRECHARGE command (10)
CL = 3
tROH
33
tCK
CL = 2
tROH
2—
tCK
6. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced to
1.5V crossover point.
7. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
8. Timing actually specified by tWR plus tRP; clock(s) specified as a reference
only at minimum cycle rate.
9. Timing actually specified by tWR.
10. Required clocks are specified by JEDEC functionality and are not dependent
on any timing parameter.
11. JEDEC and PC100 specify three clocks.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1210BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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