參數(shù)資料
型號(hào): XC3S500E-4PQ208I
廠商: Xilinx Inc
文件頁(yè)數(shù): 146/227頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3E 208PQFP
標(biāo)準(zhǔn)包裝: 24
系列: Spartan®-3E
LAB/CLB數(shù): 1164
邏輯元件/單元數(shù): 10476
RAM 位總計(jì): 368640
輸入/輸出數(shù): 158
門數(shù): 500000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
25
Main Logic Paths
Central to the operation of each slice are two nearly
identical data paths at the top and bottom of the slice. The
description that follows uses names associated with the
bottom path. (The top path names appear in parentheses.)
The basic path originates at an interconnect switch matrix
outside the CLB. See Interconnect for more information on
the switch matrix and the routing connections.
Four lines, F1 through F4 (or G1 through G4 on the upper
path), enter the slice and connect directly to the LUT. Once
inside the slice, the lower 4-bit path passes through a LUT
‘F’ (or ‘G’) that performs logic operations. The LUT Data
output, ‘D’, offers five possible paths:
1.
Exit the slice via line “X” (or “Y”) and return to
interconnect.
2.
Inside the slice, “X” (or “Y”) serves as an input to the
DXMUX (or DYMUX) which feeds the data input, “D”, of
the FFX (or FFY) storage element. The “Q” output of the
storage element drives the line XQ (or YQ) which exits
the slice.
3.
Control the CYMUXF (or CYMUXG) multiplexer on the
carry chain.
4.
With the carry chain, serve as an input to the XORF (or
XORG) exclusive-OR gate that performs arithmetic
operations, producing a result on “X” (or “Y”).
5.
Drive the multiplexer F5MUX to implement logic
functions wider than four bits. The “D” outputs of both
the F-LUT and G-LUT serve as data inputs to this
multiplexer.
In addition to the main logic paths described above, there
are two bypass paths that enter the slice as BX and BY.
Once inside the FPGA, BX in the bottom half of the slice (or
BY in the top half) can take any of several possible
branches:
1.
Bypass both the LUT and the storage element, and
then exit the slice as BXOUT (or BYOUT) and return to
interconnect.
2.
Bypass the LUT, and then pass through a storage
element via the D input before exiting as XQ (or YQ).
3.
Control the wide function multiplexer F5MUX (or
FiMUX).
4.
Via multiplexers, serve as an input to the carry chain.
5.
Drive the DI input of the LUT.
6.
BY can control the REV inputs of both the FFY and FFX
storage elements. See Storage Element Functions.
7.
Finally, the DIG_MUX multiplexer can switch BY onto
the DIG line, which exits the slice.
The control inputs CLK, CE, SR, BX and BY have
programmable polarity. The LUT inputs do not need
programmable polarity because their function can be
inverted inside the LUT.
The sections that follow provide more detail on individual
functions of the slice.
Look-Up Tables
The Look-Up Table or LUT is a RAM-based function
generator and is the main resource for implementing logic
functions. Furthermore, the LUTs in each SLICEM pair can
be configured as Distributed RAM or a 16-bit shift register,
as described later.
Each of the two LUTs (F and G) in a slice have four logic
inputs (A1-A4) and a single output (D). Any four-variable
Boolean logic operation can be implemented in one LUT.
Functions with more inputs can be implemented by
cascading LUTs or by using the wide function multiplexers
that are described later.
The output of the LUT can connect to the wide multiplexer
logic, the carry and arithmetic logic, or directly to a CLB
output or to the CLB storage element. See Figure 18.
SHIFTOUT
SLICEM Bottom
Output
Shift data output from F-LUT RAM
CIN
SLICEL/M Bottom
Input
Carry chain input
COUT
SLICEL/M Top
Output
Carry chain output
X
SLICEL/M Bottom
Output
Combinatorial output
Y
SLICEL/M Top
Output
Combinatorial output
XB
SLICEL/M Bottom
Output
Combinatorial output from carry or F-LUT SRL16 (SLICEM)
YB
SLICEL/M Top
Output
Combinatorial output from carry or G-LUT SRL16 (SLICEM)
XQ
SLICEL/M Bottom
Output
FFX output
YQ
SLICEL/M Top
Output
FFY output
Table 10: Slice Inputs and Outputs (Cont’d)
Name
Location
Direction
Description
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XC3S500E-4PQG208C 功能描述:IC SPARTAN-3E FPGA 500K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA(23x23) 其它名稱:220-1241
XC3S500E-4PQG208I 功能描述:IC FPGA SPARTAN-3E 500K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP(28x28)
XC3S500E-4VQ100C 制造商:Xilinx 功能描述:
XC3S500E-4VQG100C 功能描述:IC FPGA SPARTAN-3E 500K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA(27x27)
XC3S500E-4VQG100I 功能描述:IC FPGA SPARTAN-3E 500K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA(27x27)