參數(shù)資料
型號(hào)： XC3S500E-4PQG208I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 177/227頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3E 500K 208-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： Spartan®-3E
LAB/CLB數(shù)： 1164
邏輯元件/單元數(shù)： 10476
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 158
門數(shù)： 500000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
配用： 122-1536-ND - KIT STARTER SPARTAN-3E
其它名稱： 122-1718
XC3S500E-4PQG208I-ND
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
53
Accommodating Input Frequencies Beyond Spec-
ified Maximums
If the CLKIN input frequency exceeds the maximum
permitted, divide it down to an acceptable value using the
CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to
“TRUE”, the CLKIN frequency is divided by a factor of two
as it enters the DCM. In addition, the CLKIN_DIVIDE_BY_2
option produces a 50% duty-cycle on the input clock,
although at half the CLKIN frequency.
Quadrant and Half-Period Phase Shift Outputs
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180, and
CLK270 outputs for 90°, 180°, and 270° phase-shifted
signals, respectively. These signals are described in
Table 28, page 48 and their relative timing is shown in
Figure 43. For control in finer increments than 90°, see
Basic Frequency Synthesis Outputs
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also
doubles the frequency, but is 180° out-of-phase with respect
to CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to
various values as described in Table 29. The basic
frequency synthesis outputs are described in Table 28.
Duty Cycle Correction of DLL Clock Outputs
The DLL output signals exhibit a 50% duty cycle, even if the
incoming CLKIN signal has a different duty cycle.
Fifty-percent duty cycle means that the High and Low times
of each clock cycle are equal.
DLL Performance Differences Between Steppings
(Module 3), the Stepping 1 revision silicon supports higher
maximum input and output frequencies. Stepping 1 devices
are backwards compatible with Stepping 0 devices.
Digital Frequency Synthesizer (DFS)
The DFS unit generates clock signals where the output
frequency is a product of the CLKIN input clock frequency
and a ratio of two user-specified integers. The two
dedicated outputs from the DFS unit, CLKFX and
CLKFX180, are defined in Table 33.
The signal at the CLKFX180 output is essentially an
inversion of the CLKFX signal. These two outputs always
exhibit a 50% duty cycle, even when the CLKIN signal does
not. The DFS clock outputs are active coincident with the
seven DLL outputs and their output phase is controlled by
the Phase Shifter unit (PS).
The output frequency (fCLKFX) of the DFS is a function of the
incoming clock frequency (fCLKIN) and two integer
attributes, as follows.
Eq 1
The CLKFX_MULTIPLY attribute is an integer ranging from
2 to 32, inclusive, and forms the numerator in Equation 1.
X-Ref Target - Figure 43
Figure 43: Characteristics of the DLL Clock Outputs
Output Signal - Duty Cycle Corrected
Phase:
Input Signal (40%/60% Duty Cycle)
0
o
90
o
180
o
270
o
0
o
90
o
180
o
270
o
0
o
DS099-2_10_101105
CLKIN
t
CLK2X
CLK2X180
CLKDV
CLK0
CLK90
CLK180
CLK270
Table 33: DFS Signals
Signal
Direction
Description
CLKFX
Output
Multiplies the CLKIN frequency by
the attribute-value ratio
(CLKFX_MULTIPLY/
CLKFX_DIVIDE) to generate a
clock signal with a new target
frequency.
CLKFX180
Output
Generates a clock signal with the
same frequency as CLKFX, but
shifted 180° out-of-phase.
f
CLKFX
f
CLKIN
CLKFX_MULTIPLY
CLKFX_DIVIDE
----------------------------------------------------
=
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XC3S500E-4VQ100C 制造商:Xilinx 功能描述:
XC3S500E-4VQG100C 功能描述:IC FPGA SPARTAN-3E 500K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC3S500E-4VQG100I 功能描述:IC FPGA SPARTAN-3E 500K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC3S500E-5CP132C 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 500K GATES 10476 CELLS 657MHZ 90NM 1.2V 132C - Trays
XC3S500E-5CPG132C 功能描述:IC FPGA SPARTAN-3E 500K 132CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
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