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| 型號： | XCCACE-TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 28/69頁 |
| 文件大小： | 0K |
| 描述： | IC ACE CONTROLLER CHIP TQ144 |
| 產(chǎn)品變化通告： | XCCACE-TQG144I Discontinuation 31/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 控制器類型： | ACE 控制器 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 30mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 管件 |
| 其它名稱： | 122-1511-5 |
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System ACE CompactFlash Solution
34
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
DATABUFREG Register (BYTE address 40h-5Fh, WORD address 20h-2Fh)
The DATABUFREG register is the portal register to the data buffer that is used to transfer data between the MPU interface
and the CompactFlash and/or Configuration controllers. The description of the DATABUFREG register bits are shown in
Test JTAG Interface (TSTJTAG)
The Test JTAG Interface (TSTJTAG) supports IEEE 1149.1
Boundary-Scan operations on the System ACE CF control-
ler and all chained FPGA devices connected to the Config-
uration JTAG (CFGJTAG) port. This interface can also be
used to program the target FPGA chain on the CFGJTAG
port, using Xilinx or third-party JTAG programming tools.
The System ACE CF controller is fully compliant with the
IEEE 1149.1 Boundary-Scan standard, commonly referred
to as JTAG. As shown in Figure 16, page 35, a Test Access
Port (TAP), instruction decoder, and the required IEEE
1149.1 Registers are included in the System ACE CF con-
troller to support the mandatory Boundary-Scan instruc-
tions. In addition, the Controller also supports an optional
32-bit identification register. Refer to the IEEE 1149.1
Boundary-Scan standard specification for a complete
description of the required instructions and detailed infor-
mation on JTAG.
When using the TSTJTAG interface as the configuration
source, the CFGTCK output of the System ACE CF
controller device is derived from the TSTTCK input. The
operating frequency of the CFGTCK is the same as
TSTTCK.
The minimum clock operating frequency is 0 MHz.
The maximum clock operating frequency is either
16.7 MHz or the maximum JTAG TCK clock speed
dictated by the devices in the JTAG chain and/or the
board design. The lowest of these values should be
used.
Table 19: DATABUFREG Register Bit Descriptions
Bit
Name
Description
0
DATA00
Data buffer portal register:
Data register bits are read-only when the DATABUFMODE bit in the STATUSREG
register is a 0, otherwise they are write-only when the DATABUFMODE bit is a 1.
DATABUFREG(07:00) are accessible in BYTE and WORD bus modes.
1DATA01
2DATA02
3DATA03
4DATA04
5DATA05
6DATA06
7DATA07
8
DATA08
Data register:
Data register bits are read-only when the DATABUFMODE bit in the STATUSREG
register is a 0, otherwise they are write-only when the DATABUFMODE bit is a 1.
DATABUFREG(15:08) are accessible in BYTE and WORD bus modes.
During BYTE bus write mode, if the data buffer is ready, any writes to the
DATABUFREG(15:08) bits cause the DATABUFREG(15:00) contents to be written to
the data buffer.
During BYTE bus read mode, if the data buffer is ready, the DATABUFREG(15:00)
register will hold the current value until the DATABUFREG(15:08) bits are read. After
DATABUFREG(15:08) is read, the DATABUFREG(15:00) register is loaded with any
pending new data.
9DATA09
10
DATA10
11
DATA11
12
DATA12
13
DATA13
14
DATA14
15
DATA15
Table 20: System ACE CF Controller TAP Pins
Pins
Description
TSTTDI (TDI)
Test Data In
TSTTDO (TDO)
Test Data Out
TSTTMS (TMS)
Test Mode Select
TSTTCK (TCK)
Test Clock
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