參數(shù)資料
型號： XCCACE-TQG144I
廠商： Xilinx Inc
文件頁數(shù)： 30/69頁
文件大?。?/td> 0K
描述： IC ACE CONTROLLER CHIP TQ144
產(chǎn)品變化通告： XCCACE-TQG144I Discontinuation 31/Oct/2011
標(biāo)準(zhǔn)包裝： 60
控制器類型： ACE 控制器
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 30mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 管件
其它名稱： 122-1511-5
System ACE CompactFlash Solution
36
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Boundary-Scan Register
The Boundary-Scan register, which is the primary test data register, is used to control and observe the state of device pins
during EXTEST and SAMPLE/PRELOAD instructions. For more information on the System ACE Boundary-Scan register
(such as bit sequence, 3-state control, and so forth), refer to the System ACE Boundary-Scan Description Language (BSDL)
file available from the software download area at: www.xilinx.com.
Bit Sequence
The bit sequence of the device is obtainable from the Boundary-Scan Description Language (BSDL) Files. These files are
available from the software download area at: www.xilinx.com.
Identification Register
The Identification Register known as the IDCODE is a fixed, vendor-assigned value that is used to electronically identify the
type of device and the manufacturer for a specific device being tested. The System ACE CF controller IDCODE register is
32 bits wide. The contents of this register can be shifted out for examination by selecting the IDCODE instruction. The
IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format,
described in Table 24.
Bypass Register
The last standard 1149.1 Boundary-Scan data register in the System ACE CF controller is the single flip-flop BYPASS
register. It directly passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized
to zero when the TAP controller is in the UPDATE-DR state.
TAP Timing Characteristics
IEEE 1149.1 boundary-scan (JTAG) testing is performed via the standard 4-wire Test Access Port (TAP). The Boundary
Scan timing waveforms and switching characteristics of the TAP are described in Figure 17 and Table 25, respectively.
Table 23: System ACE CF Controller Boundary-Scan Instructions
Boundary-Scan Instruction
Binary Code [7:0]
Description
BYPASS
11111111
Enables BYPASS
SAMPLE/PRELOAD
00000001
Enables boundary-scan SAMPLE/PRELOAD Operation
IDCODE
00001001
Enables shifting out 32-bit IDCODE
EXTEST
00000000
Enables boundary-scan EXTEST operation
Table 24: System ACE CF Controller Identification Register
Version
Family
Array Size
Manufacturer
Required by IEEE 1149.1
0000
0000001
00000000
00001001001
1
Figure 17: Test JTAG Boundary-Scan Port Timing Waveforms
0ns
50ns
100ns
150ns
2
TSTTMS
TSTTDI
TSTTCK
TSTTDO
VALID
TTCKTDO
TTAPTCK
TTCKTAP
DS080_46_030801
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