參數(shù)資料
型號(hào)： XCCACE-TQG144I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 29/69頁(yè)
文件大小： 0K
描述： IC ACE CONTROLLER CHIP TQ144
產(chǎn)品變化通告： XCCACE-TQG144I Discontinuation 31/Oct/2011
標(biāo)準(zhǔn)包裝： 60
控制器類(lèi)型： ACE 控制器
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 30mA
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 管件
其它名稱(chēng)： 122-1511-5
System ACE CompactFlash Solution
DS080 (v3.0) April 7, 2014
35
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
The JTAG signals are directly multiplexed from the respective configuration source. The TSTJTAG logic is connected to the
CFGJTAG port as long as the CompactFlash and MPU interfaces are not connected to the CFGJTAG port. Outlined in the
following sections are the details of the JTAG interface for the System ACE CF controller.
The available Boundary-Scan registers for the System ACE CF controller are shown in Table 21.
Instruction Register
The Instruction Register (IR) for the System ACE CF controller is eight bits wide and is connected between TDI and TDO
during an instruction scan sequence. The Instruction Register is parallel loaded with a fixed instruction capture pattern in
preparation for an instruction sequence. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into
the instruction register from TDI. This pattern is illustrated in Table 22.
The optional IDCODE instruction is supported in addition to the mandatory instructions (BYPASS, SAMPLE/PRELOAD, and
EXTEST). The binary values for these instructions are listed in Figure 23, page 36.
Figure 16: Test JTAG Interface Block Diagram
TAP
Controller
Logic
Identifcation Register
Instruction Register
Bypass Register
Boundary Scan Register
1
0
TSTTDI
TSTTMS
TSTTCK
CFGTDO
TSTTDO
CFGTCK
CFGTMS
CFGTDI
CFGSEL (from core)
CFGDATA (from core)
DS080_45_030801
Table 21: System ACE CF Controller Boundary-Scan Registers
Register Name
Register Length
Description
Instruction Register
8 bits
Holds current instruction OPCODE and captures internal device status.
Boundary-Scan Register
109 bits
Controls and observes input, output, and output enable.
Identification Register
32 bits
Captures device IDCODE.
Bypass Register
1 bit
Device bypass.
Table 22: Instruction Register Values Loaded into IR During Instruction Scan Sequence
IR[7]
IR[6]
IR[5]
IR[4]
IR[3]
IR[2]
IR[1:0]
CFGINSTRERR
(MPU ERRORREG
register bit)
CFGFAILED
(MPU ERRORREG
register bit)
CFGREADERR
(MPU ERRORREG
register bit)
CFCERROR
(MPU STATUSREG
register bit)
CFGERROR
(MPU STATUSREG
register bit)
CFGDONE
01
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