REV. 1.4.2 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.19 Internal Loopback The L580 UART provides " />
參數(shù)資料
型號(hào): XR16L580IL-F
廠商: Exar Corporation
文件頁數(shù): 14/49頁
文件大?。?/td> 0K
描述: IC UART FIFO 16BYTE 32QFN
標(biāo)準(zhǔn)包裝: 490
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 托盤
其它名稱: 1016-1423
XR16L580
21
REV. 1.4.2
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
2.19
Internal Loopback
The L580 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally
including automatic hardware and software flow control.
Figure 13 shows how the modem port signals are re-
configured. Transmit data from the transmit shift register output is internally routed to the receive shift register
input allowing the system to receive the same data that it was sending. The TX pin is held at logic 1 or mark
condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Caution:
the RX input pins must be held to a logic 1 during loopback test else upon exiting the loopback test the UART
may detect and report a false “break” signal.
FIGURE 13. INTERNAL LOOP BACK
TX
RX
Mo
dem
/G
en
era
lP
urp
ose
C
on
trol
L
ogic
In
ternal
D
a
ta
B
u
sLin
es
and
Control
S
ig
n
als
RTS#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTS#
DTR#
DSR#
RI#
CD#
OP1#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2#
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