參數資料
| 型號： | XR16L580IL-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 6/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16BYTE 32QFN |
| 標準包裝： | 490 |
| 通道數： | 1，UART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS422 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1423 |
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XR16L580
14
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.4.2
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
Transmit
FIFO
16X Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1,2 and Xon1,2 Reg.)
TXF IF O 1
THR Interrupt (ISR bit-1):
FIFO is Enabled by FCR bit-0=1
- When the TX FIFO falls below the
programmed Trigger Level, and
- When the TX FIFO becomes empty.
2.11
RECEIVER
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. On the falling edge of a
start or a false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start
bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is
validated as a start bit. Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Each of the data, parity and stop bits is sampled at the middle of the bit to prevent false framing. If
there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte
from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status
of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character
or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.11.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XR16L580IL-F | 制造商:Exar Corporation 功能描述:IC SGL UART 3MBPS 5.5V 32-QFN |
| XR16L580ILTR | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L580ILTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L580IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
| XR16L580IM-0A-EVB | 功能描述:UART 接口集成電路 Supports L580 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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