REV. 1.4.2 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE RTS# - 21 32 O UART Request-to-Send (active low) or general p" />
參數(shù)資料
型號(hào)： XR16L580IL-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 45/49頁(yè)
文件大小： 0K
描述： IC UART FIFO 16BYTE 32QFN
標(biāo)準(zhǔn)包裝： 490
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN（5x5）
包裝： 托盤(pán)
其它名稱： 1016-1423
XR16L580
5
REV. 1.4.2
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
RTS#
-
21
32
O
UART Request-to-Send (active low) or general purpose output. This out-
put must be asserted prior to using auto RTS flow control, see EFR[6],
MCR[1] and IER[6]. This pin is not available in the 24-QFN package.
CTS#
-
24
38
I
UART Clear-to-Send (active low) or general purpose input. It can be
used for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This
input should be connected to VCC when not used. This pin is not avail-
able in the 24-QFN package.
DTR#
-
22
33
O
UART Data-Terminal-Ready (active low) or general purpose output. This
pin is not available in the 24-QFN package.
DSR#
-
25
39
I
UART Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on
the UART. This pin is not available in the 24-QFN package.
CD#
-
26
40
I
UART Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on
the UART. This pin is not available in the 24-QFN package.
RI#
-
27
41
I
UART Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on
the UART. This pin is not available in the 24-QFN package.
ANCILLARY SIGNALS
XTAL1
9
10
14
I
Crystal or external clock input. This input is not 5V tolerant.
XTAL2
10
11
15
O
Crystal or buffered clock output. This output may be use to drive a clock
buffer which can drive other device(s).
PwrSave
8
9
13
I
Power-Save (active high). This feature isolates the L580’s data bus inter-
face from the host preventing other bus activities that cause higher power
drain during sleep mode. See Sleep Mode with Auto Wake-up and
Power-Save Feature section for details. This pin has an internal pull-
down resistor in the 48-TQFP package. The 32-QFN package does not
have this pull-down resistor.
16/68#
1
2
1
I
Intel or Motorola Bus Select. This pin has an internal pull-up resistor in
the 48-TQFP package. The 32-QFN package does not have this resistor.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate in
the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will oper-
ate in the Motorola bus type of interface.
RESET
(RESET#)
18
23
35
I
When 16/68# pin is at logic 1 for Intel bus interface, this input becomes
RESET (active high). When 16/68# pin is at logic 0 for Motorola bus inter-
face, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers
and all outputs of the UART. The UART transmitter output will be held at
logic 1, the receiver input will be ignored and outputs are reset during
reset period (see UART Reset Conditions).
VCC
19
28
42
Pwr 2.25V to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.
GND
12
13
18
Pwr Power supply common, ground.
Pin Descriptions
NAME
24-QFN
PIN#
32-QFN
PIN#
48-
TQFP
PIN#
TYPE
DESCRIPTION
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