REV. 1.4.2 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE EFR[6]: Auto RTS Flow Control Enable This bit has no func" />
參數(shù)資料
型號: XR16L580IL-F
廠商: Exar Corporation
文件頁數(shù): 29/49頁
文件大?。?/td> 0K
描述: IC UART FIFO 16BYTE 32QFN
標(biāo)準(zhǔn)包裝: 490
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 托盤
其它名稱: 1016-1423
XR16L580
35
REV. 1.4.2
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
EFR[6]: Auto RTS Flow Control Enable
This bit has no functionality in the 24-QFN package.
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at one trigger level above the programmed trigger level. RTS# will return to a logic
0 when FIFO data falls below one trigger level below the programmed trigger level. The RTS# output must be
asserted (logic 0) before the auto RTS can take effect. RTS# pin will function as a general purpose output
when hardware flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
This bit has no functionality in the 24-QFN package.
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.16
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Write Only
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, refer to
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