參數(shù)資料
型號(hào)： XR17D158IV
廠商： EXAR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
中文描述： 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁(yè)數(shù)： 26/72頁(yè)
文件大?。?/td> 1520K
代理商： XR17D158IV
XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
xr
REV. 1.2.1
26
4.0
TRANSMIT AND RECEIVE DATA
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel in the device configuration register
set to ease programming. These registers support 8, 16
,
24 and 32 bits wide format. In the 32-bit format, it
increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data
byte with its associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register
(LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates
data unloading with the error flags without having to read the LSR register separately. Furthermore, the
XR17D158 supports PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the
data byte.
4.1
FIFO
DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS
IN 32-BIT FORMAT.
The XR17D158 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the 16550 register set) where the RX and the TX FIFO can be read from/written to, as
shown in
Table 3
. The following is an extract from the table showing the burstable memory locations:
Channel N: (for channels 0 through 7) where M = 2N + 1.
RX FIFO
:
0xM00 - 0xM3F (64 bytes)
TX FIFO
:
0xM00 - 0xM3F (64 bytes)
RX FIFO + status
:
0xM80 - 0xMFF (64 bytes data + 64 bytes status)
For example, the locations for channel 2 are:
Channel 2:
RX FIFO
:
0x500 - 0x53F (64 bytes)
TX FIFO
:
0x500 - 0x53F (64 bytes)
RX FIFO + status
:
0x580 - 0x5FF (64 bytes data + 64 bytes status)
4.1.1
Normal Rx FIFO
Data Unloading at locations 0x100, 0x300, 0x500, 0x700
The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel
2),......., 0xF00 (channel 7). This operation is at least 16 times faster than reading the data in 64 separate 8-bit
memory reads of RHR register (0x000 for channel 0, 0x200 for channel 1, 0x400 for channel 2,......, 0xE00 for
channel 7).
R
EAD
RX FIFO,
WITH N
O
E
RRORS
B
YTE
3
B
YTE
2
B
YTE
1
B
YTE
0
Read n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Read n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
相關(guān)PDF資料
PDF描述
XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
XR17D158CV UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
XR17L152IM CAP .068UF 400V PEN FILM 2825 5%
XR17L152 3.3V PCI BUS DUAL UART
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR17D158IV-F 功能描述:UART 接口集成電路 3.3V-5V 64B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17D158IVTR-F 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17D158IVTR-F
XR17L152 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3.3V PCI BUS DUAL UART
XR17L152CM 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3.3V PCI BUS DUAL UART
XR17L152IM 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3.3V PCI BUS DUAL UART
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