參數(shù)資料
型號: XR17D158IV
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
中文描述: 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁數(shù): 51/72頁
文件大小: 1520K
代理商: XR17D158IV
xr
REV. 1.2.1
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
XR17D158
51
5.8.14
Enhanced features are enabled or disabled using this register. Bits 0-3 provide single or dual consecutive
character software flow control selection (see
Table 19
). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits. See
Table 19
for complete
selections. The XOFF1/XOFF2 characters are transmitted approximately 2 character times after the RX FIFO
level has reached the RX trigger level, irrespective of which trigger table is used (Trigger Tables A-D). The
XON1/XON2 characters are transmitted when the RX FIFO level falls below the next lower trigger level for
Trigger Tables A-C and they are transmitted when the RX FIFO level falls below the (RX trigger level -
hysteresis level) for Trigger Table D. For example, if Trigger Table D is used with an RX trigger level of 56 and
a hysteresis level of 16, the XON1/XON2 characters are sent when the RX FIFO level count falls below 40.
Enhanced Feature Register (EFR) - Read/Write
T
ABLE
18: 16 S
ELECTABLE
H
YSTERESIS
L
EVELS
W
HEN
T
RIGGER
T
ABLE
-D
IS
S
ELECTED
FCTR B
IT
-3
FCTR B
IT
-2
FCTR B
IT
-1
FCTR B
IT
-0
RTS/DTR H
YSTERESIS
(
CHARACTERS
)
0
0
0
0
0
0
0
0
1
± 4
0
0
1
0
± 6
0
0
1
1
± 8
0
1
0
0
± 8
0
1
0
1
± 16
0
1
1
0
± 24
0
1
1
1
± 32
1
1
0
0
± 12
1
1
0
1
± 20
1
1
1
0
± 28
1
1
1
1
± 36
1
0
0
0
± 40
1
0
0
1
± 44
1
0
1
0
± 48
1
0
1
1
± 52
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