參數(shù)資料
型號(hào)： XR17D158IV
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
中文描述： 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁(yè)數(shù)： 69/72頁(yè)
文件大小： 1520K
代理商： XR17D158IV
xr
REV. 1.2.1
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
XR17D158
69
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2004 EXAR Corporation
Datasheet November 2004.
Send your UART technical inquiry with technical details to hotline:
uarttechsupport@exar.com
.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
D
ATE
R
EVISION
D
ESCRIPTION
May 2003
1.0.0
Final Production Release. Updated AC and DC specifications. Clarified PCI
Burst Read and Write Transactions.
July 2003
1.1.0
Added Device Status to Ordering Information.
June 2004
1.2.0
Clarified pin descriptions- changed from using logic 1 and logic 0 to HIGH
(VCC) and LOW (GND) for input and output pin descriptions. Clarified Auto
RS485 and Sleep Mode description. Added timing diagram for external
clock input at XTAL1 pin (
Figure 19
) and T
ECLK
, T
ECH
, and T
ECL
to AC Elec-
trical Specifications. The Device Revision Register (DREV) has been
updated to 0x03 for devices with top mark date code "C2 YYWW".
November 2004
1.2.1
The Device Revision Register (DREV) has been updated to 0x09 for devices
with top mark date code "I2 YYWW".
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