參數(shù)資料
型號: XR17D158IV
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
中文描述: 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁數(shù): 38/72頁
文件大小: 1520K
代理商: XR17D158IV
XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
xr
REV. 1.2.1
38
1
0
1
0
TXTRG - Transmit FIFO Trigger Level
Write-only
1
0
1
1
RXCNT - Receive FIFO Level Counter
Read-only
1
0
1
1
RXTRG - Receive FIFO Trigger Level
Write-only
1
1
0
0
Xoff-1 - Xoff Character 1
Write-only
1
1
0
0
Xchar
Read-only
Xon,Xoff Rcvd. Flags
1
1
0
1
Xoff-2 - Xoff Character 2
Write-only
1
1
1
0
Xon-1 - Xon Character 1
Write-only
1
1
1
1
Xon-2 - Xon Character 2
Write-only
T
ABLE
13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
BY
EFR B
IT
-4.
A
DDRESS
A3-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
0 0 0 0
RHR
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0 0 0 0
THR
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0 0 0 0
DLL
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0 0 0 1
DLM
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0 0 0 1
IER
R/W
0/
0/
0/
0
Modem
Status Int.
Enable
RX Line
Status Int.
Enable
TX Empty
Int.
Enable
RX Data
Int.
Enable
CTS/
DSR# Int.
Enable
RTS/
DTR# Int.
Enable
Xon/Xoff/
Sp. Char.
Int.
Enable
0 0 1 0
ISR
R
FIFOs
Enable
FIFOs
Enable
0/
0/
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
Delta-
Flow Cntl
Xoff/special
char
0 0 1 0
FCR
W
RX FIFO
Trigger
RX FIFO
Trigger
0/
0/
DMA
Mode
TX FIFO
Reset
RX FIFO
Reset
FIFOs
Enable
TX FIFO
Trigger
TX FIFO
Trigger
0 0 1 1
LCR
R/W
Divisor
Enable
Set TX
Break
Set Parity Even Par-
ity
Parity
Enable
Stop Bits
Word
Length
Bit-1
Word
Length
Bit-0
0 1 0 0
MCR
R/W
0/
0/
0/
Internal
Lopback
Enable
(OP2)
1
(OP1)
1
RTS# Pin
Control
DTR# Pin
Control
BRG
Prescaler
IR
Enable
XonAny
RTS/DTR
Flow Sel
0 1 0 1
LSR
R/W
RX FIFO
E
RROR
TSR
Empty
THR
Empty
RX Break
RX Fram-
ing Error
RX Parity
Error
RX Over-
run
RX Data
Ready
0 1 1 0
MSR
R
CD
RI
DSR
CTS
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
MSR
W
RS485
DLY-3
RS485
DLY-2
RS485
DLY-1
RS485
DLY-0
Reserved Reserved Reserved Reserved
T
ABLE
12: UART CHANNEL CONFIGURATION REGISTERS
A
DDRESS
R
EGISTER
R
EAD
/W
RITE
C
OMMENTS
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