參數(shù)資料
型號(hào): XR17L152
廠商: Exar Corporation
英文描述: 3.3V PCI BUS DUAL UART
中文描述: 3.3V的PCI總線雙UART
文件頁(yè)數(shù): 21/55頁(yè)
文件大?。?/td> 318K
代理商: XR17L152
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
á
DISCONTINUED
21
4.1
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2
16
-1) to obtain a 16X or 8X sampling clock of the
serial data rate. The sampling clock is used by the transmitter for data bit shifting and
receiver for data
sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the
BRG must be programmed during initialization to the operating data rate.
Programmable Baud Rate Generator
Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the
operating data rate.
Table 9
shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. At 8X sampling rate, these data rates would double. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated with the following equation(s).
F
IGURE
8. B
AUD
R
ATE
G
ENERATOR
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16),
WITH
8XMODE [1:0]
IS
0
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8),
WITH
8XMODE [1:0]
IS
1
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X
Sampling
Rate Clock to
Transmitter
and Receiver
To Channel 1
Baud Rate
Generator
Logic
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