XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
á
DISCONTINUED
41
FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select
These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is
selected (FCTR bit-6 and 7 are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger
level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control.
Table 16
below shows the 16 selectable hysteresis levels.
FCTR[4]: Infrared RX Input Logic Select
Logic 0 = Select RX input as active high encoded IrDA data, normal, (default).
Logic 1 = Select RX input as active low encoded IrDA data, inverted.
FCTR[5]: Auto RS485 Enable
This bit overrides the EN485# pin selection.
Auto RS485 half duplex control enable/disable.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from 1 to 0
when finished sending the last stop bit of the last character out of the TSR register. It changes back to logic
level 1 from 0 when a data byte is loaded into the THR or transmit FIFO. The change to logic 1 occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
T
ABLE
16: 16 S
ELECTABLE
H
YSTERESIS
L
EVELS
W
HEN
T
RIGGER
T
ABLE
-D
IS
S
ELECTED
FCTR B
IT
-3 FCTR B
IT
-2 FCTR B
IT
-1 FCTR B
IT
-0
RTS/DTR H
YSTERESIS
(
CHARACTERS
)
0
0
0
0
0
0
0
0
1
+/- 4
0
0
1
0
+/- 6
0
0
1
1
+/- 8
0
1
0
0
+/- 8
0
1
0
1
+/- 16
0
1
1
0
+/- 24
0
1
1
1
+/- 32
1
1
0
0
+/- 12
1
1
0
1
+/- 20
1
1
1
0
+/- 28
1
1
1
1
+/- 36
1
0
0
0
+/- 40
1
0
0
1
+/- 44
1
0
1
0
+/- 48
1
0
1
1
+/- 52