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參數(shù)資料
| 型號： | XR17L152 |
| 廠商： | Exar Corporation |
| 英文描述： | 3.3V PCI BUS DUAL UART |
| 中文描述： | 3.3V的PCI總線雙UART |
| 文件頁數(shù)： | 30/55頁 |
| 文件大?。?/td> | 318K |
| 代理商： | XR17L152 |
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DISCONTINUED
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
30
4.7.1
Receiver Operation in non-FIFO Mode
4.7.2
Receiver Operation with FIFO
4.8
Receive Holding Register (RHR)
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. The RHR is also part of the receive FIFO of 64
bytes by 11-bit wide, 3 extra bits are for the error tags in LSR. When the FIFO is enabled by FCR bit-0, the
RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is
loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR
bits 1-4.
Registers
F
IGURE
14. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
F
IGURE
15. R
ECEIVER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
R eceive D ata S hift
R egister (R S R )
R eceive
D ata B yte
and E rrors
R H R Interrupt (IS R bit-2)
R eceive D ata
H olding R egister
(R H R )
16X or 8X C lock
(8X M O D E R egister)
R eceive D ata C haracters
D ata B it
V alidation
E rror
Tags in
LS R bits
3:1
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Sampling
Clock (8XMODE Reg.)
E
(
E
L
64 bytes by 11-
bit wide FIFO
Receive Data Characters
FIFO Trigger=48
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Data fills to 56
Data falls to 40
Data Bit
Validation
Receive Data
FIFO
(64-byte)
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) is programmed at
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# re-asserts when data falls below the
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR17L152CM | 3.3V PCI BUS DUAL UART |
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| XR2002CN | High-Voltage, High-Current Darlington Transistor Arrays |
| XR2003 | High-Voltage, High-Current Darlington Transistor Arrays |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17L152CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L152IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L154 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
| XR17L154CV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| XR17L154IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
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