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參數(shù)資料
| 型號： | XR17L152 |
| 廠商： | Exar Corporation |
| 英文描述： | 3.3V PCI BUS DUAL UART |
| 中文描述： | 3.3V的PCI總線雙UART |
| 文件頁數(shù)： | 37/55頁 |
| 文件大?。?/td> | 318K |
| 代理商： | XR17L152 |
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XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
á
DISCONTINUED
37
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Modem Control Register (MCR) or General Purpose Outputs Control
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Pins
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the
modem interface is not used, this output may be used for general purpose.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Pins
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If
the modem interface is not used, this output may be used for general purpose.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: DTR# or RTS# for Auto Flow Control
The OP1 output is not available in the XR17L152. It is present for 16C550 compatibility during internal
loopback. See
Figure 11
. Logic zero is default.
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit-6.
Logic 0 = Uses RTS#/CTS# pins for auto hardware flow control.
Logic 1 = Uses DTR#/DSR# pin is used for auto hardware flow control.
MCR[3]: (OP2)
The OP2 output is not available in the XR17L152. It is present for 16C550 compatibility during internal
loopback. See
Figure 11
. Logic zero is default.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Figure 11
.
MCR[5]: Xon-Any Enable
Logic 0 = Disable Xon-Any function (for 16C550 compatibility) (default).
Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data
transmission.
MCR[6]: Infrared Encoder/Decoder Enable
This bit overrides the ENIR pin selection.
Logic 0 = Disable the infrared mode (default).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/
input are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle
data conditions. FCTR bit-4 may be selected to invert the RX input signal level going to the decoder for
infrared modules that provide rather an inverted output.
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PDF描述 |
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| XR17L152CM | 3.3V PCI BUS DUAL UART |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR17L152CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L152IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L154 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
| XR17L154CV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| XR17L154IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
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