REV. 1.0.3 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is sp" />
參數(shù)資料
型號: XR19L402IL48-0B-EB
廠商: Exar Corporation
文件頁數(shù): 24/49頁
文件大小: 0K
描述: EVAL BOARD FOR XR19L402-B 48QFN
標準包裝: 1
系列: *
XR19L402
30
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. 1.0.3
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
0
No parity
0
1
Odd parity
0
1
Even parity
1
0
1
Force parity to mark, “1”
1
Forced parity to space, “0”
BIT-2
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