REV. 1.0.3 TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER and control registers (MSR/MCR), programmable data rate (clock) diviso" />
參數(shù)資料
型號： XR19L402IL48-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 49/49頁
文件大小： 0K
描述： EVAL BOARD FOR XR19L402-B 48QFN
標準包裝： 1
系列： *
XR19L402
9
REV. 1.0.3
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user
accessible Scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the L402 offers enhanced feature registers, namely,
EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR and FC that provide Xon/Xoff software flow control, FIFO
trigger level control and FIFO level counters. All the register functions are discussed in full detail later in
2.7
INT (IRQ#) Output
The interrupt output changes according to the operating mode and enhanced features setup. Table 3 and
Table 4 below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola
modes. Also see Figures 19 through 22.
TABLE 3: INT (IRQ#) PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
(I/M# = 1)
0 = one byte in THR
1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
IRQ# Pin
(I/M# = 0)
1 = one byte in THR
0 = THR empty
1 = FIFO above trigger level
0 = FIFO below trigger level or FIFO empty
TABLE 4: INT (IRQ#) PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INT Pin
(I/M# = 1)
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
IRQ# Pin
(I/M# = 0)
1 = no data
0 = 1 byte
1 = FIFO below trigger level
0 = FIFO above trigger level
2.8
Crystal or External Clock Input
The L402 includes an on-chip oscillator (XTAL1 and XTAL2) to generate a clock when a crystal is connected
between the XTAL1 and XTAL2 pins of the device. Alternatively, an external clock can be supplied through the
XTAL1 pin. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock input and XTAL2 pin is the bufferred output which can be used as a clock signal for
other devices in the system. Please note that the input XTAL1 is not 5V tolerant and therefore, the maximum
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