TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B DLM, DLL DLM = 0x00 and DLL " />
參數(shù)資料
型號： XR19L402IL48-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 33/49頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR19L402-B 48QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B
DLM, DLL
DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up.
They do not reset when the Reset Pin is asserted.
DLD
Bits 7-0 = 0x00
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
EMSR
Bits 7-0 = 0x80
FLVL
Bits 7-0 = 0x00
TRG
Bits 7-0 = 0x00
FC
Bits 7-0 = 0x00
FCTR
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
TXA/TXB
RS-485 LOW
RXA/RXB
RS-485 LOW
TXB
CMOS/TTL HIGH (or VCC)
INT
(IRQ#)
Three-State Condition (16 mode)
CMOS/TTL HIGH (68 mode)
XR19L402
39
REV. 1.0.3
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REGISTERS
RESET STATE
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