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參數(shù)資料
| 型號： | XR19L402IL48-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 32/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR19L402-B 48QFN |
| 標準包裝： | 1 |
| 系列： | * |
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XR19L402
38
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. 1.0.3
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, and DLD
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-
7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5,
MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[7:5]: Reserved
For normal operation, these bits should be at logic 0.
4.19.1
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 7.
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