XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
á
PRELIMINARY
IV
T
X
E3 TTB-5 R
EGISTER
(A
DDRESS
= 0
X
3D) .......................................................................................... 113
T
X
E3 TTB-6 R
EGISTER
(A
DDRESS
= 0
X
3E) ........................................................................................... 113
T
X
E3 TTB-7 R
EGISTER
(A
DDRESS
= 0
X
3F) ........................................................................................... 113
T
X
E3 TTB-8 R
EGISTER
(A
DDRESS
= 0
X
40) ........................................................................................... 114
T
X
E3 TTB-9 R
EGISTER
(A
DDRESS
= 0
X
41) ........................................................................................... 114
T
X
E3 TTB-10 R
EGISTER
(A
DDRESS
= 0
X
42) ......................................................................................... 115
T
X
E3 TTB-11 R
EGISTER
(A
DDRESS
= 0
X
43) ......................................................................................... 115
T
X
E3 TTB-12 R
EGISTER
(A
DDRESS
= 0
X
44) ......................................................................................... 115
T
X
E3 TTB-13 R
EGISTER
(A
DDRESS
= 0
X
45) ......................................................................................... 116
T
X
E3 TTB-14 R
EGISTER
(A
DDRESS
= 0
X
46) ......................................................................................... 116
T
X
E3 TTB-15 R
EGISTER
(A
DDRESS
= 0
X
47) ......................................................................................... 116
T
X
E3 FA1 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
48) ......................................................................... 117
T
X
E3 FA2 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
49) ......................................................................... 117
T
X
E3 BIP-8 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
4A) ...................................................................... 117
2.4.7 Transmit E3 Framer Configuration Registers (ITU-T G.751) ................................................................. 118
T
X
E3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30) ............................................................................ 118
T
X
E3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) .................................................................. 119
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ...................................................... 120
T
X
E3 S
ERVICE
B
ITS
R
EGISTER
(A
DDRESS
= 0
X
35) ................................................................................ 121
T
X
E3 FAS E
RROR
M
ASK
R
EGISTER
- 0 (A
DDRESS
= 0
X
48) ................................................................... 121
T
X
E3 FAS E
RROR
M
ASK
R
EGISTER
- 1 (A
DDRESS
= 0
X
49) ................................................................... 121
T
X
E3 BIP-4 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
4A) ...................................................................... 122
2.4.8 Performance Monitor Registers ............................................................................................................. 122
PMON LCV E
VENT
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
51) ........................................................... 122
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
52) ................................... 123
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
53) .................................... 123
PMON P
ARITY
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
54) ..................................................... 123
PMON P
ARITY
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
55) ...................................................... 123
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
56) ........................................................ 124
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
57) ......................................................... 124
PMON CP-B
IT
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
58) ..................................................... 124
PMON CP-B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
59) ...................................................... 125
PMON H
OLDING
R
EGISTER
(A
DDRESS
= 0
X
6C) ..................................................................................... 125
O
NE
-S
ECOND
E
RROR
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
6D) ................................................................ 125
LCV - O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
= 0
X
6E) ............................................ 126
LCV - O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
= 0
X
6F) .............................................. 126
F
RAME
P
ARITY
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
= 0
X
70) ................ 126
F
RAME
P
ARITY
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
= 0
X
71) ................. 127
F
RAME
CP-B
IT
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
= 0
X
72) ............... 127
F
RAME
P
ARITY
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
= 0
X
73) ................. 127
L
INE
I
NTERFACE
D
RIVE
R
EGISTER
(A
DDRESS
= 0
X
80) ............................................................................ 128
L
INE
I
NTERFACE
S
CAN
R
EGISTER
(A
DDRESS
= 0
X
81) ............................................................................. 130
HDLC C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
82) ..................................................................................... 131
2.5 T
HE
L
OSS
OF
C
LOCK
E
NABLE
F
EATURE
............................................................................................................. 131
A
DDRESS
= 0
X
01, F
RAMER
I/O C
ONTROL
R
EGISTER
.............................................................................. 132
2.6 U
SING
THE
PMON H
OLDING
R
EGISTER
.............................................................................................................. 132
2.7 T
HE
I
NTERRUPT
S
TRUCTURE
WITHIN
THE
F
RAMER
M
ICROPROCESSOR
I
NTERFACE
S
ECTION
................................. 132
T
ABLE
6: L
IST
OF
ALL
OF
THE
P
OSSIBLE
C
ONDITIONS
THAT
CAN
G
ENERATE
I
NTERRUPTS
WITHIN
EACH
CHANNEL
OF
THE
XRT72L58 F
RAMER
D
EVICE
...................................................................................................... 133
T
ABLE
7: A L
ISTING
OF
THE
XRT72L58 F
RAMER
D
EVICE
I
NTERRUPT
B
LOCK
R
EGISTERS
(
FOR
DS3 A
PPLICA
-
TIONS
) ................................................................................................................................................... 133
T
ABLE
8: A L
ISTING
OF
THE
XRT72L58 F
RAMER
D
EVICE
I
NTERRUPT
B
LOCK
R
EGISTERS
(
FOR
E3, ITU-T G.832
A
PPLICATIONS
) ...................................................................................................................................... 133
T
ABLE
9: A L
ISTING
OF
THE
XRT72L58 F
RAMER
D
EVICE
I
NTERRUPT
B
LOCK
R
EGISTER
(
FOR
E3, ITU-T G.751
A
PPLICATIONS
) ...................................................................................................................................... 134