XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
á
PRELIMINARY
REV. P1.1.2
61
Address Bus into its internal circuitry. At this
point, the initial address of the burst access has
now been selected.
A.5
Further, the μC/μP should indicate that this
cycle is a Read cycle by setting the
WR_R/W
(R/W*) input pin "High".
A.6
Next the μC/μP should initiate the current bus
cycle by toggling the RD_DS (Data Strobe)
input pin "Low". This step will enable the bi-
directional data bus output drivers, within the
XRT72L58 DS3/E3 Framer device. At this
point, the bi-directional data bus output drivers
will proceed to driver the contents of the
Address register onto the bi-directional data
bus.
A.7
After some settling time, the data on the bi-
directional data bus will stabilize and can be
read by the μC/μP The XRT72L58 DS3/E3
Framer will indicate that this data can be read
by asserting the
RDY_DTCK
(DTACK) signal.
A.8
After the μC/μP detects the
RDY_DTCK
signal
(from the XRT72L58 DS3/E3 Framer) it will ter-
minate the Read Cycle by toggling the RD_DS
(Data Strobe) input pin "High".
Figure 33 presents an illustration of the behavior of
the Microprocessor Interface Signals during the initial
Read Operation, within a Burst I/O Cycle, for a Motor-
ola-type μC/μP
At the completion of this initial read cycle, the μC/μP
has read in the contents of the first register or buffer
location (within the XRT72L58 DS3/E3 Framer) for
this particular burst access operation. In order to il-
lustrate how this burst I/O cycle works, the byte (or
word) of data, that is being read in Figure 33 has
been labeled Valid Data at Offset = 0x00. This indi-
cates that the μC/μP is reading the very first register
(or buffer location) in this burst access.
2.3.2.2.2.1.2
The Subsequent Read Operations
The procedure that the μC/μP must use to perform
the remaining read cycles, within this Burst Access
operation, is presented below.
B.0
Execute each subsequent Read Cycle, as
described in steps B.1 through B.3, below.
B.1
Without toggling the ALE_AS input pin (e.g.,
keeping it "High"), toggle the RD_DS (Data
Strobe) input pin "Low". This step accom-
plishes the following.
a.
The Framer internally increments the latched
address value (within the Microprocessor Inter-
face circuitry).
b.
The output drivers of the bi-directional data bus
(D[7:0]) are enabled. At some time later, the reg-
ister or buffer location corresponding to the incre-
mented latched address value will be driven onto
the bi-directional data bus.
N
OTE
:
In order to insure that the XRT72L58 DS3/E3
Framer device will interpret this signal as being a Read sig-
nal, the
μC/μP
should keep the WR_R/W input pin "High".
F
IGURE
33. B
EHAVIOR
OF
THE
M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
,
DURING
THE
I
NITIAL
R
EAD
O
PERATION
OF
A
B
URST
C
YCLE
(M
OTOROLA
T
YPE
P
ROCESSOR
)
ALE_AS
A(11:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Not Valid
Address of "Initial" Target Register (Offset = 0x00)
Valid Data at
Offset = 0x00